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| author | Nick Clifton <nickc@redhat.com> | 2000-12-02 00:55:22 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2000-12-02 00:55:22 +0000 |
| commit | 84ea6cf2c5170547163a4bf09ac2bbb3cd424685 (patch) | |
| tree | 1fb075a0ae4d0564fa882e22e5fad7cb13c0de9a /include/opcode | |
| parent | 481294f002ca17aecedd61f586ddef21b278a634 (diff) | |
| download | gdb-84ea6cf2c5170547163a4bf09ac2bbb3cd424685.zip gdb-84ea6cf2c5170547163a4bf09ac2bbb3cd424685.tar.gz gdb-84ea6cf2c5170547163a4bf09ac2bbb3cd424685.tar.bz2 | |
Add MIPS V and MIPS 64 machine numbers
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/ChangeLog | 3 | ||||
| -rw-r--r-- | include/opcode/mips.h | 5 |
2 files changed, 8 insertions, 0 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index ceb0317..798d303 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -25,6 +25,9 @@ (OPCODE_IS_MEMBER): Update for new ISA membership-related constant meanings. + * mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New + definitions. + 2000-10-20 Jakub Jelinek <jakub@redhat.com> * sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B. diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 7eaba30..bd8f023 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -313,6 +313,7 @@ struct mips_opcode #define INSN_ISA4 0x00000080 #define INSN_ISA5 0x00000100 #define INSN_ISA32 0x00000200 +#define INSN_ISA64 0x00000400 /* Chip specific instructions. These are bitmasks. */ @@ -334,7 +335,9 @@ struct mips_opcode #define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2) #define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3) #define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4) +#define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5) #define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32) +#define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64) /* CPU defines, use instead of hardcoding processor number. Keep this in sync with bfd/archures.c in order for machine selection to work. */ @@ -357,6 +360,8 @@ struct mips_opcode #define CPU_MIPS16 16 #define CPU_MIPS32 32 #define CPU_MIPS32_4K 3204113 /* 32, 04, octal 'K' */ +#define CPU_MIPS5 5 +#define CPU_MIPS64 64 /* Test for membership in an ISA including chip specific ISAs. INSN is pointer to an element of the opcode table; ISA is the |