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| author | Elena Zannoni <ezannoni@kwikemart.cygnus.com> | 2002-08-19 20:55:48 +0000 |
|---|---|---|
| committer | Elena Zannoni <ezannoni@kwikemart.cygnus.com> | 2002-08-19 20:55:48 +0000 |
| commit | 0449635dbddc52294aa49c18e38f324a4676162b (patch) | |
| tree | 82398df7db10f586109cded57baeee35330027f5 /include/opcode/ppc.h | |
| parent | 21283bebca94b284a78853af888f11f7861e6928 (diff) | |
| download | gdb-0449635dbddc52294aa49c18e38f324a4676162b.zip gdb-0449635dbddc52294aa49c18e38f324a4676162b.tar.gz gdb-0449635dbddc52294aa49c18e38f324a4676162b.tar.bz2 | |
2002-08-19 Elena Zannoni <ezannoni@redhat.com>
From matthew green <mrg@redhat.com>
* ppc.h (PPC_OPCODE_SPE): New opcode flag for Powerpc e500
instructions.
(PPC_OPCODE_ISEL, PPC_OPCODE_BRLOCK, PPC_OPCODE_PMR,
PPC_OPCODE_CACHELCK, PPC_OPCODE_RFMCI): New opcode flags for the
e500x2 Integer select, branch locking, performance monitor,
cache locking and machine check APUs, respectively.
(PPC_OPCODE_EFS): New opcode type for efs* instructions.
(PPC_OPCODE_CLASSIC): New opcode type for Classic PowerPC instructions.
Diffstat (limited to 'include/opcode/ppc.h')
| -rw-r--r-- | include/opcode/ppc.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h index f7db66f..ffd313a 100644 --- a/include/opcode/ppc.h +++ b/include/opcode/ppc.h @@ -107,6 +107,30 @@ extern const int powerpc_num_opcodes; /* Opcode isn't supported by Power4 architecture. */ #define PPC_OPCODE_NOPOWER4 (040000) +/* Opcode is only supported by POWERPC Classic architecture. */ +#define PPC_OPCODE_CLASSIC (0100000) + +/* Opcode is only supported by e500x2 Core. */ +#define PPC_OPCODE_SPE (0200000) + +/* Opcode is supported by e500x2 Integer select APU. */ +#define PPC_OPCODE_ISEL (0400000) + +/* Opcode is an e500 SPE floating point instruction. */ +#define PPC_OPCODE_EFS (01000000) + +/* Opcode is supported by branch locking APU. */ +#define PPC_OPCODE_BRLOCK (02000000) + +/* Opcode is supported by performance monitor APU. */ +#define PPC_OPCODE_PMR (04000000) + +/* Opcode is supported by cache locking APU. */ +#define PPC_OPCODE_CACHELCK (010000000) + +/* Opcode is supported by machine check APU. */ +#define PPC_OPCODE_RFMCI (020000000) + /* A macro to extract the major opcode from an instruction. */ #define PPC_OP(i) (((i) >> 26) & 0x3f) |