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author | Maciej W. Rozycki <macro@linux-mips.org> | 2012-07-06 14:20:22 +0000 |
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committer | Maciej W. Rozycki <macro@linux-mips.org> | 2012-07-06 14:20:22 +0000 |
commit | 9d7b4c23ac400d653e62d98d18877f0779480d4d (patch) | |
tree | fc860c4808116618bcd3bf9437fbc9b1ce98aefd /include/opcode/mips.h | |
parent | 9bfc60bf8d4cddf04d1ec55e17fb22480da862c1 (diff) | |
download | gdb-9d7b4c23ac400d653e62d98d18877f0779480d4d.zip gdb-9d7b4c23ac400d653e62d98d18877f0779480d4d.tar.gz gdb-9d7b4c23ac400d653e62d98d18877f0779480d4d.tar.bz2 |
* mips.h: Fix a typo in description.
Diffstat (limited to 'include/opcode/mips.h')
-rw-r--r-- | include/opcode/mips.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/opcode/mips.h b/include/opcode/mips.h index fb9094c..9232508 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -1646,7 +1646,7 @@ extern const int bfd_mips16_num_opcodes; "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3) "z" must be zero register "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ) - "B" 8-bit syscall/wait function code (MICROMIPSOP_*_CODE10) + "B" 10-bit syscall/wait function code (MICROMIPSOP_*_CODE10) "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS) "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes |