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| author | Richard Sandiford <rdsandiford@googlemail.com> | 2013-07-07 10:15:09 +0000 |
|---|---|---|
| committer | Richard Sandiford <rdsandiford@googlemail.com> | 2013-07-07 10:15:09 +0000 |
| commit | 5c324c169bf9735f120bf2f64a671aa7285574ad (patch) | |
| tree | 67b3c6b87217f4f902e4d465ebbcc337f7978027 /include/opcode/mips.h | |
| parent | 23e69e47b4cb274e848e0f06e240cdf43b8e0a69 (diff) | |
| download | gdb-5c324c169bf9735f120bf2f64a671aa7285574ad.zip gdb-5c324c169bf9735f120bf2f64a671aa7285574ad.tar.gz gdb-5c324c169bf9735f120bf2f64a671aa7285574ad.tar.bz2 | |
include/opcode/
* mips.h: Remove documentation of "[" and "]". Update documentation
of "k" and the MDMX formats.
opcodes/
* mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
MDMX-like instructions.
* mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
printing "Q" operands for INSN_5400 instructions.
gas/
* config/tc-mips.c (validate_mips_insn): Remove "[" and "]" handling.
(mips_ip): Likewise. Do not set is_mdmx for INSN_5400 instructions.
Check constraints on the VR5400 RZU.OB, SLL.OB and SRL.OB instructions.
gas/testsuite/
* gas/mips/vr5400-ill.s, gas/mips/vr5400-ill.l: New test.
* gas/mips/mips.exp: Run it.
Diffstat (limited to 'include/opcode/mips.h')
| -rw-r--r-- | include/opcode/mips.h | 18 |
1 files changed, 8 insertions, 10 deletions
diff --git a/include/opcode/mips.h b/include/opcode/mips.h index b583a51..f70a500 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -387,7 +387,6 @@ struct mips_opcode "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) "j" 16 bit signed immediate (OP_*_DELTA) "k" 5 bit cache opcode in target register position (OP_*_CACHE) - Also used for immediate operands in vr5400 vector insns. "o" 16 bit signed offset (OP_*_DELTA) "p" 16 bit PC relative branch target address (OP_*_DELTA) "q" 10 bit extra breakpoint code (OP_*_CODE2) @@ -446,7 +445,6 @@ struct mips_opcode "P" 5 bit performance-monitor register (OP_*_PERFREG) "e" 5 bit vector register byte specifier (OP_*_VECBYTE) "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) - see also "k" above Macro instructions: "A" General 32 bit expression @@ -457,13 +455,14 @@ struct mips_opcode "f" 32 bit floating point constant "l" 32 bit floating point constant in .lit4 - MDMX instruction operands (note that while these use the FP register - fields, they accept both $fN and $vN names for the registers): - "O" MDMX alignment offset (OP_*_ALN) - "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) - "X" MDMX destination register (OP_*_FD) - "Y" MDMX source register (OP_*_FS) - "Z" MDMX source register (OP_*_FT) + MDMX and VR5400 instruction operands (note that while these use the + FP register fields, the MDMX instructions accept both $fN and $vN names + for the registers): + "O" alignment offset (OP_*_ALN) + "Q" vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) + "X" destination register (OP_*_FD) + "Y" source register (OP_*_FS) + "Z" source register (OP_*_FT) DSP ASE usage: "2" 2 bit unsigned immediate for byte align (OP_*_BP) @@ -526,7 +525,6 @@ struct mips_opcode Other: "()" parens surrounding optional value "," separates operands - "[]" brackets around index for vector-op scalar operand specifier (vr5400) "+" Start of extension sequence. Characters used so far, for quick reference when adding more: |