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| author | Thiemo Seufer <ths@networkno.de> | 2001-08-16 19:24:33 +0000 |
|---|---|---|
| committer | Thiemo Seufer <ths@networkno.de> | 2001-08-16 19:24:33 +0000 |
| commit | 99c14723f3f437e55488c8819241d359414ec9d6 (patch) | |
| tree | a2d0bdc6122e67dcf915754adb1f2bf637292921 /include/opcode/mips.h | |
| parent | 2cd8959083e24196760ddf35310c6c8d88ba00df (diff) | |
| download | gdb-99c14723f3f437e55488c8819241d359414ec9d6.zip gdb-99c14723f3f437e55488c8819241d359414ec9d6.tar.gz gdb-99c14723f3f437e55488c8819241d359414ec9d6.tar.bz2 | |
Add support for MIPS R1[02]000 performance counter opcodes.
Diffstat (limited to 'include/opcode/mips.h')
| -rw-r--r-- | include/opcode/mips.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 23e6028..349d266 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -326,6 +326,8 @@ struct mips_opcode #define INSN_4100 0x00040000 /* Toshiba R3900 instruction. */ #define INSN_3900 0x00080000 +/* MIPS R10000 instruction. */ +#define INSN_10000 0x00100000 /* MIPS ISA defines, use instead of hardcoding ISA level. */ @@ -375,7 +377,9 @@ struct mips_opcode || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ || ((cpu == CPU_VR4100 || cpu == CPU_R4111) \ && ((insn)->membership & INSN_4100) != 0) \ - || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)) + || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ + || ((cpu == CPU_R10000 || cpu == CPU_R12000) \ + && ((insn)->membership & INSN_10000) != 0)) /* This is a list of macro expanded instructions. |