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| author | Andrew Bennett <andrew.bennett@imgtec.com> | 2013-12-16 07:19:34 -0800 |
|---|---|---|
| committer | Andrew Bennett <andrew.bennett@imgtec.com> | 2013-12-16 07:43:20 -0800 |
| commit | e269fea784da752b49b5fc406ee7ea8403955a28 (patch) | |
| tree | 3772ebf657a4355834f582bfffe0e5e3fd775cf5 /include/opcode/mips.h | |
| parent | 9a362b9a3291ef43316e1606e2b26fe55ebb187f (diff) | |
| download | gdb-e269fea784da752b49b5fc406ee7ea8403955a28.zip gdb-e269fea784da752b49b5fc406ee7ea8403955a28.tar.gz gdb-e269fea784da752b49b5fc406ee7ea8403955a28.tar.bz2 | |
Range of element index is too large on MIPS MSA element selection instructions.
The element index range for the following MIPS MSA instructions: sldi, splati,
copy_s, copy_u, insert and insve is 1 bit too large. This patch fixes this issue.
ChangeLog:
gas/testsuite/gas/mips/
* msa.s: Reduced maximum element index range for sldi, splati,
copy_s, copy_u, insert and insve instructions.
* msa64.s: Likewise.
* micromips@msa.d: Likewise.
* micromips@msa64.d: Likewise.
* msa.d: Likewise.
* msa64.d: Likewise.
include/opcode/
* mips.h: Updated description of +o, +u, +v and +w for MIPS and
microMIPS.
opcodes/
* micromips-opc.c (decode_micromips_operand): Reduced range of +o, +u,
+v and +w.
(micromips_opcodes): Reduced element index range for sldi, splati,
copy_s, copy_u, insert and insve instructions.
* opcodes/mips-opc.c (decode_mips_operand): Reduced range of +o, +u,
+v and +w.
(mips_builtin_opcodes): Reduced element index range for sldi, splati,
copy_s, copy_u, insert and insve instructions.
Diffstat (limited to 'include/opcode/mips.h')
| -rw-r--r-- | include/opcode/mips.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/include/opcode/mips.h b/include/opcode/mips.h index c9dc52b..7ea0900 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -910,10 +910,10 @@ struct mips_opcode "+k" 5-bit GPR at bit 6 "+l" 5-bit MSA control register at bit 6 "+n" 5-bit MSA control register at bit 11 - "+o" 5-bit vector element index at bit 16 - "+u" 4-bit vector element index at bit 16 - "+v" 3-bit vector element index at bit 16 - "+w" 2-bit vector element index at bit 16 + "+o" 4-bit vector element index at bit 16 + "+u" 3-bit vector element index at bit 16 + "+v" 2-bit vector element index at bit 16 + "+w" 1-bit vector element index at bit 16 "+T" (-512 .. 511) << 0 at bit 16 "+U" (-512 .. 511) << 1 at bit 16 "+V" (-512 .. 511) << 2 at bit 16 @@ -2093,10 +2093,10 @@ extern const int bfd_mips16_num_opcodes; "+k" 5-bit GPR at bit 6 "+l" 5-bit MSA control register at bit 6 "+n" 5-bit MSA control register at bit 11 - "+o" 5-bit vector element index at bit 16 - "+u" 4-bit vector element index at bit 16 - "+v" 3-bit vector element index at bit 16 - "+w" 2-bit vector element index at bit 16 + "+o" 4-bit vector element index at bit 16 + "+u" 3-bit vector element index at bit 16 + "+v" 2-bit vector element index at bit 16 + "+w" 1-bit vector element index at bit 16 "+x" 5-bit shift amount at bit 16 "+T" (-512 .. 511) << 0 at bit 16 "+U" (-512 .. 511) << 1 at bit 16 |