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| author | H.J. Lu <hjl.tools@gmail.com> | 2012-09-04 13:52:06 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2012-09-04 13:52:06 +0000 |
| commit | b3e14edafcdc558d724452ee5b803ff096c32d0f (patch) | |
| tree | 44a3814f838c0bdf05c27616bfc7828962d33eb9 /include/opcode/ia64.h | |
| parent | c6d8cab4ac5c906937dcd4f884e65fb4d1052381 (diff) | |
| download | gdb-b3e14edafcdc558d724452ee5b803ff096c32d0f.zip gdb-b3e14edafcdc558d724452ee5b803ff096c32d0f.tar.gz gdb-b3e14edafcdc558d724452ee5b803ff096c32d0f.tar.bz2 | |
Add Intel Itanium Series 9500 support
bfd/
2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
* cpu-ia64-opc.c (ins_cnt6a): New function.
(ext_cnt6a): Ditto.
(ins_strd5b): Ditto.
(ext_strd5b): Ditto.
(elf64_ia64_operands): Add new operand types.
gas/
2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
* config/tc-ia64.c (reg_symbol): Add a new register.
(indirect_reg): Ditto.
(pseudo_func): Add new symbolic constants.
(operand_match): Add new operand types recognition.
(operand_insn): Add new register recognition.
(md_begin): Add new register definition.
(specify_resource): Add new register recognition.
gas/testsuite/
2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
* gas/testsuite/gas/ia64/psn.d: New file.
* gas/testsuite/gas/ia64/psn.s: New file.
* gas/testsuite/gas/ia64/ia64.exp: Add new testcase.
* gas/testsuite/gas/ia64/opc-i.d: Fixed failing tests.
* gas/testsuite/gas/ia64/opc-m.d: Ditto.
include/opcode/
2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
* ia64.h (ia64_opnd): Add new operand types.
opcodes/
2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
* ia64-asmtab.h (completer_index): Extend bitfield to full uint.
* ia64-gen.c: Promote completer index type to longlong.
(irf_operand): Add new register recognition.
(in_iclass_mov_x): Add an entry for the new mov_* instruction type.
(lookup_specifier): Add new resource recognition.
(insert_bit_table_ent): Relax abort condition according to the
changed completer index type.
(print_dis_table): Fix printf format for completer index.
* ia64-ic.tbl: Add a new instruction class.
* ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions.
* ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions.
* ia64-opc.h: Define short names for new operand types.
* ia64-raw.tbl: Add new RAW resource for DAHR register.
* ia64-waw.tbl: Add new WAW resource for DAHR register.
* ia64-asmtab.c: Regenerate.
Diffstat (limited to 'include/opcode/ia64.h')
| -rw-r--r-- | include/opcode/ia64.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/include/opcode/ia64.h b/include/opcode/ia64.h index 4285377..433c505 100644 --- a/include/opcode/ia64.h +++ b/include/opcode/ia64.h @@ -91,6 +91,7 @@ enum ia64_opnd IA64_OPND_R2, /* second register # */ IA64_OPND_R3, /* third register # */ IA64_OPND_R3_2, /* third register # (limited to gr0-gr3) */ + IA64_OPND_DAHR3, /* dahr reg # ( bits 23-25) */ /* memory operands: */ IA64_OPND_MR3, /* memory at addr of third register # */ @@ -105,6 +106,7 @@ enum ia64_opnd IA64_OPND_PKR_R3, /* pkr[reg] */ IA64_OPND_PMC_R3, /* pmc[reg] */ IA64_OPND_PMD_R3, /* pmd[reg] */ + IA64_OPND_DAHR_R3, /* dahr[reg] */ IA64_OPND_RR_R3, /* rr[reg] */ /* immediate operands: */ @@ -134,7 +136,9 @@ enum ia64_opnd IA64_OPND_IMM9a, /* signed 9-bit immediate (bits 6-12, 27, 36) */ IA64_OPND_IMM9b, /* signed 9-bit immediate (bits 13-19, 27, 36) */ IA64_OPND_IMM14, /* signed 14-bit immediate (bits 13-19, 27-32, 36) */ + IA64_OPND_IMMU16, /* unsigned 16-bit immediate (bits 6-9, 12-22, 36) */ IA64_OPND_IMM17, /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */ + IA64_OPND_IMMU19, /* unsigned 19-bit immediate (bits 6-9, 12-25, 36) */ IA64_OPND_IMMU21, /* unsigned 21-bit immediate (bits 6-25, 36) */ IA64_OPND_IMM22, /* signed 22-bit immediate (bits 13-19, 22-36) */ IA64_OPND_IMMU24, /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */ @@ -155,6 +159,9 @@ enum ia64_opnd IA64_OPND_TGT64, /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */ IA64_OPND_LDXMOV, /* any symbol, generates R_IA64_LDXMOV. */ + IA64_OPND_CNT6a, /* 6-bit count (bits 6-11) */ + IA64_OPND_STRD5b, /* 5-bit stride (bits 13-17) */ + IA64_OPND_COUNT /* # of operand types (MUST BE LAST!) */ }; @@ -191,6 +198,7 @@ enum ia64_resource_specifier IA64_RS_CR_IRR, IA64_RS_CR_LRR, IA64_RS_CR, /* 3-7,10-15,18,28-63,75-79,82-127 */ + IA64_RS_DAHR, IA64_RS_DBR, IA64_RS_FR, IA64_RS_FRb, @@ -212,6 +220,7 @@ enum ia64_resource_specifier IA64_RS_PSR, /* PSR bits */ IA64_RS_RSE, /* implementation-specific RSE resources */ IA64_RS_AR_FPSR, + }; enum ia64_rse_resource |