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authorH.J. Lu <hjl.tools@gmail.com>2006-02-27 15:35:37 +0000
committerH.J. Lu <hjl.tools@gmail.com>2006-02-27 15:35:37 +0000
commit331d2d0d9ce1220133395ba0172b371aec077c16 (patch)
tree7d035e233d226ebf0859ade38eee0da347c430eb /include/opcode/i386.h
parent22edb2f16480aef5e060ad021199c3086300a4f5 (diff)
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gas/
2006-02-27 H.J. Lu <hongjiu.lu@intel.com> * gas/config/tc-i386.c (output_insn): Support Intel Merom New Instructions. * gas/config/tc-i386.h (CpuMNI): New. (CpuUnknownFlags): Add CpuMNI. gas/testsuite/ 2006-02-27 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Add merom and x86-64-merom. * gas/i386/merom.d: New file. * gas/i386/merom.s: Likewise. * gas/i386/x86-64-merom.d: Likewise. * gas/i386/x86-64-merom.s: Likewise. include/opcode/ 2006-02-27 H.J. Lu <hongjiu.lu@intel.com> * i386.h (i386_optab): Support Intel Merom New Instructions. opcodes/ 2006-02-27 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by Intel Merom New Instructions. (THREE_BYTE_0): Likewise. (THREE_BYTE_1): Likewise. (three_byte_table): Likewise. (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use THREE_BYTE_1 for entry 0x3a. (twobyte_has_modrm): Updated. (twobyte_uses_SSE_prefix): Likewise. (print_insn): Handle 3-byte opcodes used by Intel Merom New Instructions.
Diffstat (limited to 'include/opcode/i386.h')
-rw-r--r--include/opcode/i386.h35
1 files changed, 35 insertions, 0 deletions
diff --git a/include/opcode/i386.h b/include/opcode/i386.h
index 33f94cc..2b2c1e0 100644
--- a/include/opcode/i386.h
+++ b/include/opcode/i386.h
@@ -1379,6 +1379,41 @@ static const template i386_optab[] =
{"vmxoff", 0, 0x0f01, 0xc4, CpuVMX, NoSuf|ImmExt, { 0, 0, 0} },
{"vmxon", 1, 0xf30fc7, 6, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64, { LLongMem, 0, 0} },
+/* Merom New Instructions. */
+
+{"phaddw", 2, 0x0f3801,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"phaddw", 2, 0x660f3801,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"phaddd", 2, 0x0f3802,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"phaddd", 2, 0x660f3802,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"phaddsw", 2, 0x0f3803,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"phaddsw", 2, 0x660f3803,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"phsubw", 2, 0x0f3805,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"phsubw", 2, 0x660f3805,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"phsubd", 2, 0x0f3806,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"phsubd", 2, 0x660f3806,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"phsubsw", 2, 0x0f3807,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"phsubsw", 2, 0x660f3807,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"pmaddubsw", 2, 0x0f3804,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"pmaddubsw", 2, 0x660f3804,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"pmulhrsw", 2, 0x0f380b,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"pmulhrsw", 2, 0x660f380b,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"pshufb", 2, 0x0f3800,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"pshufb", 2, 0x660f3800,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"psignb", 2, 0x0f3808,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"psignb", 2, 0x660f3808,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"psignw", 2, 0x0f3809,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"psignw", 2, 0x660f3809,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"psignd", 2, 0x0f380a,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"psignd", 2, 0x660f380a,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"palignr", 3, 0x0f3a0f,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX|LongMem, RegMMX } },
+{"palignr", 3, 0x660f3a0f,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
+{"pabsb", 2, 0x0f381c,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"pabsb", 2, 0x660f381c,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"pabsw", 2, 0x0f381d,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"pabsw", 2, 0x660f381d,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+{"pabsd", 2, 0x0f381e,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
+{"pabsd", 2, 0x660f381e,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
+
/* AMD 3DNow! instructions. */
{"prefetch", 1, 0x0f0d, 0, Cpu3dnow, NoSuf|IgnoreSize|Modrm, { ByteMem, 0, 0 } },