diff options
| author | Nick Clifton <nickc@redhat.com> | 2017-11-08 14:30:53 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2017-11-08 14:30:53 +0000 |
| commit | c0e7cef7156b2bc15ba43441ad14c6e83c09df8e (patch) | |
| tree | 0ea0ffa8915a6746c94f88180b5748094c46f216 /include/opcode/aarch64.h | |
| parent | dec41383fff7116c9f66cdeca3105e968047a4e6 (diff) | |
| download | gdb-c0e7cef7156b2bc15ba43441ad14c6e83c09df8e.zip gdb-c0e7cef7156b2bc15ba43441ad14c6e83c09df8e.tar.gz gdb-c0e7cef7156b2bc15ba43441ad14c6e83c09df8e.tar.bz2 | |
Split the AArch64 Crypto instructions for AES and SHA1+2 into their own options (+aes and +sha2).
The new options are:
+aes: Enables the AES instructions of Armv8-a,
enabled by default with +crypto.
+sha2: Enables the SHA1 and SHA2 instructions of Armv8-a,
enabled by default with +crypto.
These options have been turned on by default when +crypto
is used, as such no breakage is expected.
The reason for the split is because with the introduction of Armv8.4-a
the implementation of AES has explicitly been made independent of the
implementation of the other crypto extensions. Backporting the split does
not break any of the previous requirements and so is safe to do.
gas * config/tc-aarch64.c
(aarch64_features): Include AES and SHA2 in CRYPTO.
Add SHA2 and AES.
include * opcode/aarch64.h:
(AARCH64_FEATURE_SHA2, AARCH64_FEATURE_AES): New.
opcodes * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
(aarch64_feature_sha2, aarch64_feature_aes): New.
(SHA2, AES): New.
(AES_INSN, SHA2_INSN): New.
(pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
(sha1h, sha1su1, sha256su0, sha1c, sha1p,
sha1m, sha1su0, sha256h, sha256h2, sha256su1):
Change to SHA2_INS.
Diffstat (limited to 'include/opcode/aarch64.h')
| -rw-r--r-- | include/opcode/aarch64.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index ea45a41..325b757 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -37,6 +37,8 @@ extern "C" { typedef uint32_t aarch64_insn; /* The following bitmasks control CPU features. */ +#define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */ +#define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */ #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */ #define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */ #define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */ |