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| author | Jan Beulich <jbeulich@novell.com> | 2004-11-25 08:42:54 +0000 |
|---|---|---|
| committer | Jan Beulich <jbeulich@novell.com> | 2004-11-25 08:42:54 +0000 |
| commit | 37edbb65ad7d81f172315eadf4f66783d78c36a5 (patch) | |
| tree | 9113686b18a9275f5a46f1c0ecd9d38d2b7dcb64 /include/opcode/ChangeLog | |
| parent | ebd98106b23a4d1d64a492cf26977e66c32393ac (diff) | |
| download | gdb-37edbb65ad7d81f172315eadf4f66783d78c36a5.zip gdb-37edbb65ad7d81f172315eadf4f66783d78c36a5.tar.gz gdb-37edbb65ad7d81f172315eadf4f66783d78c36a5.tar.bz2 | |
gas/
2004-11-25 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (optimize_imm): Adjust immediates to only those
permissible for the selected instruction suffix.
(process_suffix): For DefaultSize instructions, suppressing the
guessing of a 'q' suffix if the instruction doesn't support it is
pointless, because only an 'l' suffix can be guessed in this place.
gas/testsuite/
2004-11-25 Jan Beulich <jbeulich@novell.com>
* gas/i386/x86-64-inval.[sl]: Remove sahf/lahf.
include/opcode/
2004-11-25 Jan Beulich <jbeulich@novell.com>
* i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
to/from test registers are illegal in 64-bit mode. Add missing
NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
(previously one had to explicitly encode a rex64 prefix). Re-enable
lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
Diffstat (limited to 'include/opcode/ChangeLog')
| -rw-r--r-- | include/opcode/ChangeLog | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 14bd353..513236f 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,4 +1,13 @@ -2004-11-23 Jan Beulich <jbeulich@novell.com> +2004-11-25 Jan Beulich <jbeulich@novell.com> + + * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves + to/from test registers are illegal in 64-bit mode. Add missing + NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix + (previously one had to explicitly encode a rex64 prefix). Re-enable + lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings + support it there. Add cmpxchg16b as per Intel's 64-bit documentation. + +2004-11-23 Jan Beulich <jbeulich@novell.com> * i386.h (i386_optab): paddq and psubq, even in their MMX form, are available only with SSE2. Change the MMX additions introduced by SSE @@ -35,7 +44,7 @@ (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and SIZE_FIELD_UNSIGNED. -2004-11-04 Jan Beulich <jbeulich@novell.com> +2004-11-04 Jan Beulich <jbeulich@novell.com> * i386.h (sldx_Suf): Remove. (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize. |