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| author | Andrew Burgess <andrew.burgess@embecosm.com> | 2018-12-04 11:48:42 +0000 |
|---|---|---|
| committer | Andrew Burgess <andrew.burgess@embecosm.com> | 2018-12-11 11:36:52 +0000 |
| commit | 99e1a184a791d30c09a86d6eca4528dc146c2c79 (patch) | |
| tree | a93f9626946d8aec365af5b66891bc5dea60ae54 /include/ChangeLog | |
| parent | 8970c0224e3c36c565672089e38de42765e87f47 (diff) | |
| download | gdb-99e1a184a791d30c09a86d6eca4528dc146c2c79.zip gdb-99e1a184a791d30c09a86d6eca4528dc146c2c79.tar.gz gdb-99e1a184a791d30c09a86d6eca4528dc146c2c79.tar.bz2 | |
gdb/riscv: Update test to handle targets without an fpu
The FPU is optional on RISC-V. The gdb.base/float.exp test currently
assumes that an fpu is always available on RISC-V. Update the test so
that this is not the case.
gdb/testsuite/ChangeLog:
* gdb.base/float.exp: Handle RISC-V targets without an FPU.
Diffstat (limited to 'include/ChangeLog')
0 files changed, 0 insertions, 0 deletions