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| author | Han Shen <shenhan@google.com> | 2015-10-27 15:17:54 -0700 |
|---|---|---|
| committer | Han Shen <shenhan@google.com> | 2015-10-27 15:22:41 -0700 |
| commit | 4d2f5d5824be99326c2c3e459c298e338856d8c8 (patch) | |
| tree | 86315d04362705eafbd5d89d658908e94b02163f /gold | |
| parent | b80c3053162ec5533e120ee4e4ed30296d4c5fb2 (diff) | |
| download | gdb-4d2f5d5824be99326c2c3e459c298e338856d8c8.zip gdb-4d2f5d5824be99326c2c3e459c298e338856d8c8.tar.gz gdb-4d2f5d5824be99326c2c3e459c298e338856d8c8.tar.bz2 | |
Patch for PR gold/19042 - unsupported reloc 311/312.
gold/
* aarch64.cc (Target_aarch64::Scan::local): Add support for
reloc 311/312.
Diffstat (limited to 'gold')
| -rw-r--r-- | gold/ChangeLog | 7 | ||||
| -rw-r--r-- | gold/aarch64.cc | 23 |
2 files changed, 30 insertions, 0 deletions
diff --git a/gold/ChangeLog b/gold/ChangeLog index 46a0636..dc1c0ea 100644 --- a/gold/ChangeLog +++ b/gold/ChangeLog @@ -1,3 +1,10 @@ +2015-10.27 Han Shen <shenhan@google.com> + + PR gold/19042 - unsupported reloc 311/312. + + * aarch64.cc (Target_aarch64::Scan::local): Add support for + reloc 311/312. + 2015-10-22 H.J. Lu <hongjiu.lu@intel.com> * x86_64.cc (Target_x86_64<size>::Scan::get_reference_flags): diff --git a/gold/aarch64.cc b/gold/aarch64.cc index 2e3c42a..275d94c 100644 --- a/gold/aarch64.cc +++ b/gold/aarch64.cc @@ -5987,6 +5987,29 @@ Target_aarch64<size, big_endian>::Scan::local( case elfcpp::R_AARCH64_PREL16: break; + case elfcpp::R_AARCH64_ADR_GOT_PAGE: + case elfcpp::R_AARCH64_LD64_GOT_LO12_NC: + // This pair of relocations is used to access a specific GOT entry. + { + bool is_new = false; + // This symbol requires a GOT entry. + if (is_ifunc) + is_new = got->add_local_plt(object, r_sym, GOT_TYPE_STANDARD); + else + is_new = got->add_local(object, r_sym, GOT_TYPE_STANDARD); + if (is_new && parameters->options().output_is_position_independent()) + target->rela_dyn_section(layout)-> + add_local_relative(object, + r_sym, + elfcpp::R_AARCH64_RELATIVE, + got, + object->local_got_offset(r_sym, + GOT_TYPE_STANDARD), + 0, + false); + } + break; + case elfcpp::R_AARCH64_LD_PREL_LO19: // 273 case elfcpp::R_AARCH64_ADR_PREL_LO21: // 274 case elfcpp::R_AARCH64_ADR_PREL_PG_HI21: // 275 |