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authorYao Qi <yao.qi@linaro.org>2016-02-26 15:00:36 +0000
committerYao Qi <yao.qi@linaro.org>2016-02-26 15:00:36 +0000
commit9fde51ed303ea3ecbaa7c0084ea417e775a5db29 (patch)
tree6b10ff7bd7975f837fec66d4437d03da95269e8d /gold
parent1f33efec7c6d1357d7e867176cfb88942fc513a8 (diff)
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Fix various bugs in arm_record_exreg_ld_st_insn
This patch fixes various bugs in arm_record_exreg_ld_st_insn, and use gdb.reverse/insn-reverse.c to test more arm instructions. - Set flag SINGLE_REG correctly. In the arch reference manual, SING_REG is true when the bit 8 of instruction is zero. - Record the right D registers for instructions changing S registers. - Fix the order of length and address in record_buf_mem array. - Shift the offset by 2 instead of by 24. This patch also fixes one internal error, (gdb) PASS: gdb.reverse/finish-precsave.exp: BP at end of main continue^M Continuing.^M ../../binutils-gdb/gdb/utils.c:1072: internal-error: virtual memory exhausted.^M A problem internal to GDB has been detected,FAIL: gdb.reverse/finish-precsave.exp: run to end of main (GDB internal error) gdb: 2016-02-26 Yao Qi <yao.qi@linaro.org> * arm-tdep.c (arm_record_exreg_ld_st_insn): Set 'single_reg' per bit 8. Check bit 20 instead of bit 4 for VMOV instruction. Record D registers for instructions changing S registers. Change of the order of length and address in record_buf_mem array. gdb/testsuite: 2016-02-26 Yao Qi <yao.qi@linaro.org> * gdb.reverse/insn-reverse.c [__arm__] (ext_reg_load): New. [__arm__] (ext_reg_mov, ext_reg_push_pop): New. (testcases): Update.
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