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author | Ian Lance Taylor <ian@airs.com> | 2009-12-30 06:57:17 +0000 |
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committer | Ian Lance Taylor <ian@airs.com> | 2009-12-30 06:57:17 +0000 |
commit | 1a2dff539bff0b85f89b2f8f0c30dab1851f59a5 (patch) | |
tree | 549fd584889a912f8d7aec63610c52b2969dee96 /gold/powerpc.cc | |
parent | f0ba79e29c2b6fd25f66a9c1050cd09f6e069513 (diff) | |
download | gdb-1a2dff539bff0b85f89b2f8f0c30dab1851f59a5.zip gdb-1a2dff539bff0b85f89b2f8f0c30dab1851f59a5.tar.gz gdb-1a2dff539bff0b85f89b2f8f0c30dab1851f59a5.tar.bz2 |
* layout.cc (Layout::Layout): Initialize increase_relro_.
(Layout::get_output_section): Add is_relro, is_last_relro, and
is_first_non_relro parameters. Change all callers.
(Layout::choose_output_section): Likewise.
(Layout::add_output_section_data): Likewise.
(Layout::make_output_section): Likewise.
(Layout::set_segment_offsets): Clear increase_relro when using a
linker script.
* layout.h (class Layout): Add increase_relro method. Add
increase_relro_ field. Update declarations.
* output.cc (Output_section::Output_section): Initialize
is_last_relro_ and is_first_non_relro_.
(Output_segment::add_output_section): Group relro sections is
do_sort is true. Handle is_last_relro and is_first_non_relro.
(Output_segment::maximum_alignment): Remove relro handling.
(Output_segment::set_section_addresses): Add increase_relro
parameter. Change all callers. Add initial alignment to align
relro sections on separate page. Remove old relro handling.
(Output_segment::set_section_list_addresses): Remove in_relro
parameter. Change all callers.
(Output_segment::set_offset): Add increase parameter. Change all
callers. Remove old relro handling.
* output.h (class Output_section): Add new methods: is_last_relro,
set_is_last_relro, is_first_non_relro, set_is_first_non_relro.
Add is_last_relro_ and is_first_non_relro_ fields.
* i386.cc (Target_i386::got_section): Don't call set_is_relro.
Create separate .got.plt section. Call increase_relro.
* x86_64.cc (Target_x86_64::got_section): Likewise.
* testsuite/relro_script_test.t: Add .got.plt.
Diffstat (limited to 'gold/powerpc.cc')
-rw-r--r-- | gold/powerpc.cc | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/gold/powerpc.cc b/gold/powerpc.cc index f27a9f1..f7e62e7 100644 --- a/gold/powerpc.cc +++ b/gold/powerpc.cc @@ -716,7 +716,7 @@ Target_powerpc<size, big_endian>::got_section(Symbol_table* symtab, layout->add_output_section_data(".got", elfcpp::SHT_PROGBITS, elfcpp::SHF_ALLOC | elfcpp::SHF_WRITE, - this->got_, false); + this->got_, false, false, false, false); // Create the GOT2 or TOC in the .got section. if (size == 32) @@ -725,7 +725,8 @@ Target_powerpc<size, big_endian>::got_section(Symbol_table* symtab, layout->add_output_section_data(".got2", elfcpp::SHT_PROGBITS, elfcpp::SHF_ALLOC | elfcpp::SHF_WRITE, - this->got2_, false); + this->got2_, false, false, false, + false); } else { @@ -733,7 +734,8 @@ Target_powerpc<size, big_endian>::got_section(Symbol_table* symtab, layout->add_output_section_data(".toc", elfcpp::SHT_PROGBITS, elfcpp::SHF_ALLOC | elfcpp::SHF_WRITE, - this->toc_, false); + this->toc_, false, false, false, + false); } // Define _GLOBAL_OFFSET_TABLE_ at the start of the .got section. @@ -760,7 +762,8 @@ Target_powerpc<size, big_endian>::rela_dyn_section(Layout* layout) gold_assert(layout != NULL); this->rela_dyn_ = new Reloc_section(parameters->options().combreloc()); layout->add_output_section_data(".rela.dyn", elfcpp::SHT_RELA, - elfcpp::SHF_ALLOC, this->rela_dyn_, true); + elfcpp::SHF_ALLOC, this->rela_dyn_, true, + false, false, false); } return this->rela_dyn_; } @@ -820,7 +823,8 @@ Output_data_plt_powerpc<size, big_endian>::Output_data_plt_powerpc(Layout* layou { this->rel_ = new Reloc_section(false); layout->add_output_section_data(".rela.plt", elfcpp::SHT_RELA, - elfcpp::SHF_ALLOC, this->rel_, true); + elfcpp::SHF_ALLOC, this->rel_, true, false, + false, false); } template<int size, bool big_endian> @@ -949,7 +953,7 @@ Target_powerpc<size, big_endian>::make_plt_entry(Symbol_table* symtab, (elfcpp::SHF_ALLOC | elfcpp::SHF_EXECINSTR | elfcpp::SHF_WRITE), - this->plt_, false); + this->plt_, false, false, false, false); // Define _PROCEDURE_LINKAGE_TABLE_ at the start of the .plt section. symtab->define_in_output_data("_PROCEDURE_LINKAGE_TABLE_", NULL, @@ -1512,7 +1516,8 @@ Target_powerpc<size, big_endian>::scan_relocs( Output_section* os = layout->add_output_section_data(".sdata", 0, elfcpp::SHF_ALLOC | elfcpp::SHF_WRITE, - sdata, false); + sdata, false, + false, false, false); symtab->define_in_output_data("_SDA_BASE_", NULL, Symbol_table::PREDEFINED, os, |