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| author | Maciej W. Rozycki <macro@imgtec.com> | 2017-05-12 01:09:36 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@imgtec.com> | 2017-05-12 01:12:10 +0100 |
| commit | a4f89915135f6760917c01dc783de5b674234d84 (patch) | |
| tree | 7361b054783a02df06643a4e1cd23e0607fb4680 /gold/mips.cc | |
| parent | de428bc53335d88c21eda38a823d5a4008468e52 (diff) | |
| download | gdb-a4f89915135f6760917c01dc783de5b674234d84.zip gdb-a4f89915135f6760917c01dc783de5b674234d84.tar.gz gdb-a4f89915135f6760917c01dc783de5b674234d84.tar.bz2 | |
MIPS16/opcodes: Make the handling of BREAK and SDBBP consistent
Disassemble the MIPS16 BREAK and SDBBP instruction's immediate operand
in the hexadecimal rather than decimal numeral system and add respective
operandless variants with an implicit 0 operand, making our handling of
these instructions consistent with how we have processed their regular
MIPS and microMIPS counterparts since forever.
opcodes/
* mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
type to hexadecimal.
(mips16_opcodes): Add operandless "break" and "sdbbp" entries.
binutils/
* testsuite/binutils-all/mips/mips16-extend-insn.d: Adjust BREAK
and SDBBP disassembly.
gas/
* testsuite/gas/mips/mips16.d: Adjust BREAK disassembly.
* testsuite/gas/mips/mips16-64@mips16.d: Likewise.
* testsuite/gas/mips/mips16-64.d: Likewise.
* testsuite/gas/mips/mips16-64@mips16-64.d: Likewise.
* testsuite/gas/mips/mips16-macro.d: Likewise.
* testsuite/gas/mips/mips16-64@mips16-macro.d: Likewise.
* testsuite/gas/mips/mips16-sub.d: Likewise.
* testsuite/gas/mips/mips16-32@mips16-sub.d: Likewise.
Diffstat (limited to 'gold/mips.cc')
0 files changed, 0 insertions, 0 deletions