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| author | Christophe Lyon <christophe.lyon@arm.com> | 2022-04-01 10:21:58 +0100 |
|---|---|---|
| committer | Christophe Lyon <christophe.lyon@arm.com> | 2022-04-27 15:18:17 +0100 |
| commit | fcaa1071d7921c4f7c7592a10ed7b84830ec8c49 (patch) | |
| tree | 0f89661c8d52a54be61315da68e6b84f195809a9 /gdb | |
| parent | 41b96eef5f1de451e5e95cca053df0550f66bbf5 (diff) | |
| download | gdb-fcaa1071d7921c4f7c7592a10ed7b84830ec8c49.zip gdb-fcaa1071d7921c4f7c7592a10ed7b84830ec8c49.tar.gz gdb-fcaa1071d7921c4f7c7592a10ed7b84830ec8c49.tar.bz2 | |
gdb/arm: Fix prologue analysis to support vpush
While working on adding support for Non-secure/Secure modes unwinding,
I noticed that the prologue analysis lacked support for vpush, which
is used for instance in the CMSE stub routine.
This patch updates thumb_analyze_prologue accordingly, adding support
for vpush of D-registers.
Signed-off-by: Christophe Lyon <christophe.lyon@foss.st.com>
Signed-off-by: Christophe Lyon <christophe.lyon@arm.com>
Diffstat (limited to 'gdb')
| -rw-r--r-- | gdb/arm-tdep.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index cc77739..66e26e6 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -902,6 +902,35 @@ thumb_analyze_prologue (struct gdbarch *gdbarch, regs[bits (insn, 0, 3)] = addr; } + /* vstmdb Rn{!}, { D-registers } (aka vpush). */ + else if ((insn & 0xff20) == 0xed20 + && (inst2 & 0x0f00) == 0x0b00 + && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) + { + /* Address SP points to. */ + pv_t addr = regs[bits (insn, 0, 3)]; + + /* Number of registers saved. */ + unsigned int number = bits (inst2, 0, 7) >> 1; + + /* First register to save. */ + int vd = bits (inst2, 12, 15) | (bits (insn, 6, 6) << 4); + + if (stack.store_would_trash (addr)) + break; + + /* Calculate offsets of saved registers. */ + for (; number > 0; number--) + { + addr = pv_add_constant (addr, -8); + stack.store (addr, 8, pv_register (ARM_D0_REGNUM + + vd + number, 0)); + } + + /* Writeback SP to account for the saved registers. */ + regs[bits (insn, 0, 3)] = addr; + } + else if ((insn & 0xff50) == 0xe940 /* strd Rt, Rt2, [Rn, #+/-imm]{!} */ && pv_is_register (regs[bits (insn, 0, 3)], ARM_SP_REGNUM)) |