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authorAndrew Burgess <andrew.burgess@embecosm.com>2019-04-17 00:31:43 +0100
committerAndrew Burgess <andrew.burgess@embecosm.com>2019-04-17 00:45:22 +0100
commitc01660c625766e848195285cc20581b9ed7ecfe2 (patch)
tree22a3976de654cbb8e5e4e5d729ea7bde0dc95206 /gdb
parentfe7e91e7764d8db4a45c9d7b3dd55cb635f44f5e (diff)
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gdb/riscv: Allow breakpoints to be created at invalid addresses
Some testsuite cases (gdb.cp/nsalias.exp for example) construct dwarf2 debug info for fake functions to test that this debug info is handled correctly. We currently get an error trying to read from an invalid address while creating breakpoints for these fake functions. Other targets allow creating breakpoints on invalid addresses, and only error when GDB actually tries to insert the breakpoints. In order to make RISC-V behave in the same way as other targets, this commit makes the failure to read memory during breakpoint creation non-fatal, we then expect to see a failure when GDB tries to insert the breakpoint, just like other targets. Tested with a riscv64-linux native testsuite run. gdb/ChangeLog: * riscv-tdep.c (riscv_breakpoint_kind_from_pc): Hanndle case where code read might fail, assume 4-byte breakpoint in that case.
Diffstat (limited to 'gdb')
-rw-r--r--gdb/ChangeLog6
-rw-r--r--gdb/riscv-tdep.c10
2 files changed, 15 insertions, 1 deletions
diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index ba1300d..f8120db 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,9 @@
+2019-04-17 Jim Wilson <jimw@sifive.com>
+ Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * riscv-tdep.c (riscv_breakpoint_kind_from_pc): Hanndle case where
+ code read might fail, assume 4-byte breakpoint in that case.
+
2019-04-15 Leszek Swirski <leszeks@google.com>
* amd64-tdep.c (amd64_classify_aggregate): Use cp_pass_by_reference
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 6370bc2..4fe07ef 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -430,7 +430,15 @@ riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
unaligned_p = true;
else
{
- /* Read the opcode byte to determine the instruction length. */
+ /* Read the opcode byte to determine the instruction length. If
+ the read fails this may be because we tried to set the
+ breakpoint at an invalid address, in this case we provide a
+ fake result which will give a breakpoint length of 4.
+ Hopefully when we try to actually insert the breakpoint we
+ will see a failure then too which will be reported to the
+ user. */
+ if (target_read_code (*pcptr, buf, 1) == -1)
+ buf[0] = 0;
read_code (*pcptr, buf, 1);
}