sh-dsp support, simulator speedup by using host byte order:

sim:
	* Makefile.in (interp.o): Depends on ppi.c .
	(ppi.c): New rule.
	* gencode.c (printonmatch, think, genopc): Deleted.
	(MAX_NR_STUFF): Now 42.
	(tab): Add SH-DSP CPU instructions.
	Amalgamate ldc / stc / lds / sts instructions with similar
	bit patterns.  Fix opcodes of stc Rm_BANK,@-<REG_N>.
	Fix semantics of lds.l @<REG_N>+,MACH (no sign extend).
	(movsxy_tab): New array.
	For movs, change MMMM field to GGGG, and mmmm field to MMMM.
	Added entries for movx, movy and parallel processing insns.
	(ppi_tab): New array.
	(qfunc): Stabilize sort.
	(expand_opcode): Handle [01][01]NN, [01][01]xx and [01][01]yy.
	Handle 'M', 'G' 's' 'X', 'a', 'Y' and 'A'.
	(dumptable): Now takes three arguments.  Changed all callers.
	Emit just one contigous jump table.
	(filltable): Now takes an argument.  Changed all callers.
	Make index static.
	(ppi_moves, expand_ppi_code, ppi_filltable, ppi_gensim): New functions.
	(gensim_caselist): New function, broken out of gensim.
	Handle opcode fields 'x', 'y', 's', 'M', 'G', 'X', 'a', and 'Y'.
	Handle ref '9'.
	(gensim): Handle 'N' in code field and '8' in refs field.
	Call gensim_caselist - twice.
	(ppi_index): New static variable.
	(main): Unsupport default action.
	Add dsp support for -x / -s option.  Add -p option.
	* interp.c (sh_jump_table, sh_dsp_table, ppi_table): Declare.
	(saved_state_type): Rearrange to allow amalgamated ldc / stc /
	lds / sts to work efficiently.
	(target_dsp): New static variable.
	(GBR, VBR, SSR, SPC, MACH, MACL): Reflect saved_state_type change.
	(FPUL, Rn_BANK, SET_Rn_BANK, M, Q, S, T, SR_BL, SR_RB): Likewise.
	(SR_MD, SR_RC, SET_SR_BIT, GET_SR, SET_RC, GET_FPSCR): Likewise.
	(RS, RE, MOD, MOD_ME, DSP_R): Likewise.
	(set_fpscr1): Likewise.  Use target_dsp to check for dsp.
	(MOD_MSi, SIG_BUS_FETCH): Deleted.
	(CREG, SREG, PR, SR_MASK_DMY, SR_MASK_DMX, SR_DMY): New macros.
	(SR_DMX, DSR, MOD_DELTA, GET_DSP_GRD): Likewise.
	(SET_MOD): Reflect saved_state_type change.  Set MOD_DELTA instead
	of MOD_MS, and encode SR_DMY / SR_DMX into high word of MOD_ME.
	(set_sr): Reflect saved_state_type change.  Fix SR_RB handling.
	Use SET_MOD.
	(MA, L, TL, TB): Now controlled by ACE_FAST.
	(SEXT32): Just cast to int.
	(SIGN32): Fixed to only shift by 31.
	(CHECK_INSN_PTR): SIGBUS at insn fetch now represented by insn_end 0.
	(ppi_insn): Declare.
	(ppi.c): Include.
	(init_dsp): Set target_dsp.  When it changes, switch end of
	sh_jump_table with sh_dsp_table.
	(sim_resume) Don't declare sh_jump_table0.  Use sh_jump_table instead.
	Don't Declare PR if it's #defined.
	Fix single-stepping (Was broken in Mar  6 16:59:10 patch).
	(sim_store_register, sim_read_register): Translate accesses to
	reflect saved_state_type change.

	* interp.c (set_sr): Set sr.
	(SET_RC, MOD, MOD_MS, MOD_ME, SET_MOD, MOD_MS, MOD_ME): New macros.
	(set_fpscr1): Don't bank-switch fpu registers when simulating sh-dsp.
	(DSP_R): Fix definition.
	(sim_resume): Remove outdated SET_SR use.

	* interp.c (saved_state): New members for struct member asregs:
	rs, re, insn_end, xram_start, yram_start.
	(struct loop_bounds): New struct.
	(SKIP_INSN): New macro.
	(get_loop_bounds): New function.
	(endianw): Renamed to global_endianw.
	(maskw): negated bits.
	(PC): Now insn_ptr.
	(SR_MASK_RC, SR_RC_INCREMENT, SR_RC, RAISE_EXCEPTION): New macros.
	(RS, RE, DSP_R, DSP_GRD, A1, A0, X0, X1, Y0, Y1, M0, A1G): Likewise.
	(M1, A0G, RIAT, PT2H, PH2T, SET_NIP, CHECK_INSN_PTR): Likewise.
	(SIG_BUS_FETCH): Likewise
	(raise_exception, riat_fast): New functions.
	(raise_buserror, sim_stop): Use raise_exception.
	(PROCESS_SPECIAL_ADDRESS): Use xram_start / yram_start.
	(BUSERROR, WRITE_BUSERROR, READ_BUSERROR):
	Reverse sense of mask argument.
	(FP_OP, set_dr): Use RAISE_EXCEPTION.
	(wlat_fast, wwat_fast, wbat_fast, rlat_fast, rwat_fast, rbat_fast):
	Declare.  Remove redundant masking.
	(wwat_fast, rwat_fast): Add argument endianw.  Changed callers.
	(MA): Updated for change pc -> PC.
	(Delay_Slot): Use RIAT.
	(empty): Deleted.
	(trap): Remove argument little_endian.  Add argument endianw.
	Changed all callers.  Use raise_exception.
	(macw): Add argument endainw.  Changed all callers.
	(init_dsp): New function, extended after broken out of init_pointers.
	(sim_resume): Replace pc with insn_ptr.  Replace little_endian with
	endianw.  Replace nia with nip.  Reverse sense of maskb / maskw /
	maskl.  Implement logic for zero-overhead loops.  Don't try to
	interpret garbage when getting a SIGBUS at insn fetch.
	(sim_open): Call init_dsp.
	* gencode.c (tab): Use SET_NIP instead of nia = .  Use PH2T / PT2H /
	RAISE_EXCEPTION where appropriate.
	Add extra cycles for brai, braf , bsr, bsrf, jmp, jsr.

	* interp.c (sim_store_register, sim_fetch_register):
	Do proper endianness switch.

	* interp.c (saved_state_type): New members for struct member asregs:
	xymem_select, xmem, ymem, xmem_offset, ymem_offset.
	(special_address): Delete.
	(BUSERROR): Now a two-argument predicate.
	(PROCESS_SPECIAL_ADDRESS, WRITE_BUSERROR, READ_BUSERROR): New macros.
	(wlat_little, wwat_little, wbat_any, wlat_big, wwat_big): Delete.
	(process_wlat_addr, process_wwat_addr): New functions.
	(process_wbat_addr, process_rlat_addr, process_rwat_addr): Likewise.
	(process_rbat_addr): Likewise.
	(wlat_fast, wwat_fast, wbat_fast): Use WRITE_BUSERROR.
	(rlat_little, rwat_little, rbat_any, rlat_big, rwat_big): Delete.
	(rlat_fast, rwat_fast, rbat_fast): Use READ_BUSERROR.
	(RWAT, RLAT, RBAT, WWAT, WLAT, WBAT): Delete SLOW versions.
	(do_rdat, trap): Delete SLOW code.
	(SEXT32, SIGN32): New macros.
	(swap, swap16): Now integer in - integer out.  Changed all callers.
	(strswaplen, strnswap): Delete SLOW versions.
	(init_pointers): Initialize dsp memory selection (preliminary).
	(sim_store_register, sim_fetch_register): Use swap instead of
	big / little endian read / write functions.

	* interp.c (maskl): Deleted.
	(endianw, endianb): New variables.
	(special_address): Now inline.
	(bp_holder): Put raising of buserror there, rename to:
	(raise_buserror).
	(BUSERROR): Now yields a value.  Changed all users.
	(wbat_big): Delete.
	(wlat_fast, wwat_fast, wbat_fast): New functions.
	(rlat_fast, rwat_fast, rbat_fast): Likewise.
	(RWAT, RLAT, RBAT, WWAT, WLAT, WBAT): Use new functions.
	(do_rdat, do_wdat): Likewise.  Take maskl argument instead of
	little_endian one.  Changed caller macros.
	(swap, swap16): Use w[rw]lat_big / w[rw]lat_little directly.
	(strswaplen, strnswap): New functions.
	(trap): Use them to fix up endian mismatches;
	disable SYS_execve and SYS_execv; fix double address translation for
	SYS_pipe and SYS_stat.
	(sym_write, sym_read): Add endianness translation.
	(sym_store_register, sym_fetch_register): Add maskl local variable.
	(sim_open): Set endianw and endianb.

gdb:

	* sh-tdep.c (sh_dsp_reg_names, sh3_dsp_reg_names): New arrays.
	(sh_processor_type_table): Add entries for bfd_mach_sh_dsp and
	 bfd_mach_sh3_dsp.
	(sh_show_regs): Floating point registers are called fr0-fr15.
	For sh4, display fpul, fpscr and fr0-fr15 / dr0-dr14 as appropriate.
	Handle sh-dsp and sh3-dsp.
	config/sh/tm-sh.h (REGISTER_VIRTUAL_TYPE): sh-dsp / sh3-dsp
	don't have floating point registers.
	(DSR_REGNUM, A0G_REGNUM, A0_REGNUM, A1G_REGNUM, A1_REGNUM): Define.
	(M0_REGNUM, M1_REGNUM, X0_REGNUM, X1_REGNUM, Y0_REGNUM): Likewise.
	(Y1_REGNUM, MOD_REGNUM, RS_REGNUM, RE_REGNUM, R0B_REGNUM): Likewise.

3 files changed, 98 insertions, 7 deletions

diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index c5c15d8..129d505a 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,17 @@
+Mon May 15 21:27:27 2000  J"orn Rennecke <amylaar@cygnus.co.uk>
+
+	* sh-tdep.c (sh_dsp_reg_names, sh3_dsp_reg_names): New arrays.
+	(sh_processor_type_table): Add entries for bfd_mach_sh_dsp and
+	 bfd_mach_sh3_dsp.
+	(sh_show_regs): Floating point registers are called fr0-fr15.
+	For sh4, display fpul, fpscr and fr0-fr15 / dr0-dr14 as appropriate.
+	Handle sh-dsp and sh3-dsp.
+	config/sh/tm-sh.h (REGISTER_VIRTUAL_TYPE): sh-dsp / sh3-dsp
+	don't have floating point registers.
+	(DSR_REGNUM, A0G_REGNUM, A0_REGNUM, A1G_REGNUM, A1_REGNUM): Define.
+	(M0_REGNUM, M1_REGNUM, X0_REGNUM, X1_REGNUM, Y0_REGNUM): Likewise.
+	(Y1_REGNUM, MOD_REGNUM, RS_REGNUM, RE_REGNUM, R0B_REGNUM): Likewise.
+
 2000-05-15  Eli Zaretskii  <eliz@is.elta.co.il>
 
 	* Makefile.in (gdbtypes.o, varobj.o): Depend on wrapper.h.
diff --git a/gdb/config/sh/tm-sh.h b/gdb/config/sh/tm-sh.h
index ad26ec1..47256ae 100644
--- a/gdb/config/sh/tm-sh.h
+++ b/gdb/config/sh/tm-sh.h
@@ -101,8 +101,10 @@ extern CORE_ADDR sh_skip_prologue PARAMS ((CORE_ADDR));
    of data in register N.  */
 
 #define REGISTER_VIRTUAL_TYPE(N) \
-	((((N) >= FP0_REGNUM && (N) <= FP15_REGNUM)	\
-	  || (N) == FPUL_REGNUM)			\
+	(((((N) >= FP0_REGNUM && (N) <= FP15_REGNUM)		\
+	   || (N) == FPUL_REGNUM)				\
+	  && TARGET_ARCHITECTURE->mach != bfd_mach_sh_dsp	\
+	  && TARGET_ARCHITECTURE->mach != bfd_mach_sh3_dsp)	\
 	 ? builtin_type_float : builtin_type_int)
 
 /* Initializer for an array of names of registers.
@@ -135,12 +137,27 @@ extern char **sh_register_names;
 #define SR_REGNUM 	22
 #define FPUL_REGNUM	23
 #define FPSCR_REGNUM	24
+#define DSR_REGNUM	24
 #define FP0_REGNUM	25
 #define FP15_REGNUM	40
+#define A0G_REGNUM	25
+#define A0_REGNUM	26
+#define A1G_REGNUM	27
+#define A1_REGNUM	28
+#define M0_REGNUM	29
+#define M1_REGNUM	30
+#define X0_REGNUM	31
+#define X1_REGNUM	32
+#define Y0_REGNUM	33
+#define Y1_REGNUM	34
+#define MOD_REGNUM	40
 #define SSR_REGNUM	41
 #define SPC_REGNUM	42
 #define R0B0_REGNUM	43
 #define R0B1_REGNUM	51
+#define RS_REGNUM	43
+#define RE_REGNUM	44
+#define R0B_REGNUM	51
 
 #define NUM_REALREGS	59
 
diff --git a/gdb/sh-tdep.c b/gdb/sh-tdep.c
index 1c98caf..941e13f 100644
--- a/gdb/sh-tdep.c
+++ b/gdb/sh-tdep.c
@@ -86,6 +86,30 @@ static char *sh3e_reg_names[] = {
   "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
   "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
 };
+
+static char *sh_dsp_reg_names[] = {
+  "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
+  "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
+  "pc",   "pr",   "gbr",  "vbr",  "mach", "macl", "sr",
+  "",     "dsr",
+  "a0g",  "a0",   "a1g",  "a1",   "m0",   "m1",   "x0",   "x1",
+  "y0",   "y1",   "",     "",     "",     "",     "",     "mod",
+  "",     "",
+  "rs",   "re",   "",     "",     "",     "",     "",     "",
+  "",     "",     "",     "",     "",     "",     "",     "",
+};
+
+static char *sh3_dsp_reg_names[] = {
+  "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
+  "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
+  "pc",   "pr",   "gbr",  "vbr",  "mach", "macl", "sr",
+  "",     "dsr",
+  "a0g",  "a0",   "a1g",  "a1",   "m0",   "m1",   "x0",   "x1",
+  "y0",   "y1",   "",     "",     "",     "",     "",     "mod",
+  "ssr",  "spc",
+  "rs",   "re",   "",     "",     "",     "",     "",     "",
+  "r0b",  "r1b",  "r2b",  "r3b",  "r4b",  "r5b",  "r6b",  "r7b",
+};
 /* *INDENT-ON* */
 
 #ifdef _WIN32_WCE
@@ -110,10 +134,18 @@ sh_processor_type_table[] =
   }
   ,
   {
+    sh_dsp_reg_names, bfd_mach_sh_dsp
+  }
+  ,
+  {
     sh3_reg_names, bfd_mach_sh3
   }
   ,
   {
+    sh3_dsp_reg_names, bfd_mach_sh3_dsp
+  }
+  ,
+  {
     sh3e_reg_names, bfd_mach_sh3e
   }
   ,
@@ -648,18 +680,21 @@ sh_show_regs (args, from_tty)
   printf_filtered ("GBR=%08lx VBR=%08lx",
 		   (long) read_register (GBR_REGNUM),
 		   (long) read_register (VBR_REGNUM));
-  if (cpu == bfd_mach_sh3 || cpu == bfd_mach_sh3e)
+  if (cpu == bfd_mach_sh3 || cpu == bfd_mach_sh3e || cpu == bfd_mach_sh3_dsp
+      || cpu == bfd_mach_sh4)
     {
       printf_filtered (" SSR=%08lx SPC=%08lx",
 		       (long) read_register (SSR_REGNUM),
 		       (long) read_register (SPC_REGNUM));
-      if (cpu == bfd_mach_sh3e)
+      if (cpu == bfd_mach_sh3e || cpu == bfd_mach_sh4)
 	{
 	  printf_filtered (" FPUL=%08lx FPSCR=%08lx",
 			   (long) read_register (FPUL_REGNUM),
 			   (long) read_register (FPSCR_REGNUM));
 	}
     }
+  if (cpu == bfd_mach_sh_dsp || cpu == bfd_mach_sh3_dsp)
+    printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
 
   printf_filtered ("\nR0-R7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
 		   (long) read_register (0),
@@ -679,9 +714,13 @@ sh_show_regs (args, from_tty)
 		   (long) read_register (13),
 		   (long) read_register (14),
 		   (long) read_register (15));
-  if (cpu == bfd_mach_sh3e)
+  if (cpu == bfd_mach_sh3e || cpu == bfd_mach_sh4)
     {
-      printf_filtered ("FP0-FP7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+      int pr = cpu == bfd_mach_sh4 && (read_register (FPSCR_REGNUM) & 0x80000);
+
+      printf_filtered ((pr
+			? "DR0-DR6  %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
+			: "FP0-FP7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
 		       (long) read_register (FP0_REGNUM + 0),
 		       (long) read_register (FP0_REGNUM + 1),
 		       (long) read_register (FP0_REGNUM + 2),
@@ -690,7 +729,9 @@ sh_show_regs (args, from_tty)
 		       (long) read_register (FP0_REGNUM + 5),
 		       (long) read_register (FP0_REGNUM + 6),
 		       (long) read_register (FP0_REGNUM + 7));
-      printf_filtered ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
+      printf_filtered ((pr
+			? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
+			: "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
 		       (long) read_register (FP0_REGNUM + 8),
 		       (long) read_register (FP0_REGNUM + 9),
 		       (long) read_register (FP0_REGNUM + 10),
@@ -700,6 +741,25 @@ sh_show_regs (args, from_tty)
 		       (long) read_register (FP0_REGNUM + 14),
 		       (long) read_register (FP0_REGNUM + 15));
     }
+  /* FIXME: sh4 has more registers */
+  if (cpu == bfd_mach_sh_dsp || cpu == bfd_mach_sh3_dsp)
+    {
+      printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
+		       (long) read_register (A0G_REGNUM) & 0xff,
+		       (long) read_register (A0_REGNUM),
+		       (long) read_register (M0_REGNUM),
+		       (long) read_register (X0_REGNUM),
+		       (long) read_register (Y0_REGNUM),
+		       (long) read_register (RS_REGNUM),
+		       (long) read_register (MOD_REGNUM));
+      printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
+		       (long) read_register (A1G_REGNUM) & 0xff,
+		       (long) read_register (A1_REGNUM),
+		       (long) read_register (M1_REGNUM),
+		       (long) read_register (X1_REGNUM),
+		       (long) read_register (Y1_REGNUM),
+		       (long) read_register (RE_REGNUM));
+    }
 }
 
 /* Function: extract_return_value