2000-05-10 Michael Snyder <msnyder@seadog.cygnus.com>

Make Sparc a Multi-Arch target. Discard PARAMS macro (require ANSI). * sparc-tdep.c: include arch-utils.h. (SPARC_HAS_FPU, FP_REGISTER_BYTES, FP_MAX_REG NUM, SPARC_INTREG_SIZE, DUMMY_REG_SAVE_OFFSET): provide multi-arch-compatible definitions. (GDB_TARGET_IS_SPARC64): make into a runtime test. (struct frame_extra_info): Define, use instead of the macro. (Many places): Use alloca instead of statically allocated buffers that depend on a multi-arch variable such as MAX_REGISTER_RAW_SIZE. (sparc_extract_struct_value_address): Accept a pointer arg instead of an array sized by REGISTER_BYTES. (examine_prologue): Accept a pointer to an array of CORE_ADDR, instead of the defunct struct frame_saved_regs. Recognize new Sparc64 store instructions as part of the prologue. Ignore the destination of a frame store when parsing the prologue (so long as it's on the stack). (sparc_push_dummy_frame): Fix incorrect buffer offset for PSTATE. (sparc_frame_find_saved_regs): Accept a ptr to an array of CORE_ADDR instead of the defunct struct frame_saved_regs. (supply_gregset): Discard unnecessary 'zerobuf': just send NULL to supply_register. Provide 4-byte offset to compensate for diff between size of the prgreg_t elements on a 64-bit host and size of the registers for a 32-bit target. Fill all inaccessible regs with zero so they won't keep being requested again and again. (fill_gregset): Handle 32/64 size difference between registers and prgreg_t. Handle as many new 64-bit regs as possible. (supply_fpregset, fill_fpregset): Attempt to handle 64-bit world. (sparc_push_arguments): Rename to sparc32_push_arguments. Copy arguments into registers as well as onto stack, so that the CALL_DUMMY (code pushed onto the target stack) is not required. (sparc_extract_return_value): Rename to sparc32_extract_return_value. (sparc_store_return_value): Use memset instead of bzero. Use write_register_gen instead of write_register_bytes. (sparclet_store_return_value): New function. (_initialize_sparc_tdep): Call register_gdbarch_init to activate the gdbarch multi-architecture system. (sp64_push_arguments): Rename to sparc64_push_arguments. Extend to store arguments in general registers as well as on stack. (sparc64_extract_return_value): Rename to sp64_extract_return_value. Use as a private function, to be called by the new external function sparc64_extract_return_value. (sparclet_extract_return_value): New function. (sparc32_stack_align, sparc64_stack_align, sparc32_register_name, sparc64_register_name, sparc_print_extra_frame_info, sparclite_register_name, sparclet_register_name, sparc_push_return_address, sparc64_use_struct_convention, sparc32_store_struct_return, sparc64_store_struct_return, sparc32_register_virtual_type, sparc64_register_virtual_type, sparc32_register_size, sparc64_register_size, sparc32_register_byte, sparc64_register_byte, sparc_gdbarch_skip_prologue, sparc_convert_to_virtual, sparc_convert_to_raw, sparc_frame_init_saved_regs, sparc_frame_address, sparc_gdbarch_fix_call_dummy, sparc_coerce_float_to_double, sparc_call_dummy_address, sparc_y_regnum, sparc_reg_struct_has_addr, sparc_intreg_size, sparc_return_value_on_stack): New functions supporting multi-arch. (sparc_gdbarch_init): New function; initialize multi-arch. (struct gdbarch_tdep): Define, use for private multi-arch data. * config/sparc/tm-sparc.h: Move definitions around, enclose with #ifdef GDB_MULTI_ARCH tests, provide some multi-arch alternate definitions. Add enums for register names, to help debugging gdb. This header file must work for non-multi-arch and for multi-arch. * config/sparc/tm-sp64.h: Add GDB_MULTI_ARCH configuration. Also add AT_ENTRY_POINT definitions for CALL_DUMMY, for non-multi-arch case. Define GDB_MULTI_ARCH. * config/sparc/tm-sparclet.h: Add GDB_MULTI_ARCH configuration. Do not define GDB_MULTI_ARCH (bfd does not correctly identify target). * config/sparc/tm-sparclite.h: Ditto. * config/sparc/tm-sun4sol2.h: Define GDB_MULTI_ARCH. * sparclet-rom.c (sparclet_regnames): Initialize explicitly, to avoid using deprecated REGISTER_NAMES macro. * Makefile.in: Let sparc-tdep.c depend on arch-utils.h.
author: Michael Snyder <msnyder@vmware.com> 2000-05-10 20:07:25 +0000
committer: Michael Snyder <msnyder@vmware.com> 2000-05-10 20:07:25 +0000
commit: 5af923b0f0e349765b08f4a92adc1030ce67ff2e (patch)
tree: 26cfced85a44350b34c8cb3e26d3a42263b349b9 /gdb
parent: d2f75a6f4097075a61f4c6d47dd095d22245eed7 (diff)
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9 files changed, 2311 insertions, 747 deletions
diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index faf01da..8ad0024 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,76 @@
+2000-05-10  Michael Snyder  <msnyder@seadog.cygnus.com>
+	Make Sparc a Multi-Arch target.  Discard PARAMS macro (require ANSI).
+	* sparc-tdep.c: include arch-utils.h.
+	(SPARC_HAS_FPU, FP_REGISTER_BYTES, FP_MAX_REG NUM, SPARC_INTREG_SIZE,
+	DUMMY_REG_SAVE_OFFSET): provide multi-arch-compatible definitions.
+	(GDB_TARGET_IS_SPARC64): make into a runtime test.
+	(struct frame_extra_info): Define, use instead of the macro.
+	(Many places): Use alloca instead of statically allocated buffers
+	that depend on a multi-arch variable such as MAX_REGISTER_RAW_SIZE.
+	(sparc_extract_struct_value_address): Accept a pointer arg instead
+	of an array sized by REGISTER_BYTES.
+	(examine_prologue): Accept a pointer to an array of CORE_ADDR, 
+	instead of the defunct struct frame_saved_regs.  Recognize new
+	Sparc64 store instructions as part of the prologue.  Ignore the
+	destination of a frame store when parsing the prologue (so long
+	as it's on the stack).
+	(sparc_push_dummy_frame): Fix incorrect buffer offset for PSTATE.
+	(sparc_frame_find_saved_regs): Accept a ptr to an array of CORE_ADDR
+	instead of the defunct struct frame_saved_regs.
+	(supply_gregset): Discard unnecessary 'zerobuf': just send NULL to
+	supply_register.  Provide 4-byte offset to compensate for diff
+	between size of the prgreg_t elements on a 64-bit host and size
+	of the registers for a 32-bit target.  Fill all inaccessible regs
+	with zero so they won't keep being requested again and again.
+	(fill_gregset): Handle 32/64 size difference between registers
+	and prgreg_t.  Handle as many new 64-bit regs as possible.
+	(supply_fpregset, fill_fpregset): Attempt to handle 64-bit world.
+	(sparc_push_arguments): Rename to sparc32_push_arguments.
+	Copy arguments into registers as well as onto stack, so that the
+	CALL_DUMMY (code pushed onto the target stack) is not required.
+	(sparc_extract_return_value): Rename to sparc32_extract_return_value.
+	(sparc_store_return_value): Use memset instead of bzero.
+	Use write_register_gen instead of write_register_bytes.
+	(sparclet_store_return_value): New function.
+	(_initialize_sparc_tdep): Call register_gdbarch_init to activate
+	the gdbarch multi-architecture system.
+	(sp64_push_arguments): Rename to sparc64_push_arguments.
+	Extend to store arguments in general registers as well as on stack.
+	(sparc64_extract_return_value): Rename to sp64_extract_return_value.
+	Use as a private function, to be called by the new external function
+	sparc64_extract_return_value.
+	(sparclet_extract_return_value): New function.
+	(sparc32_stack_align, sparc64_stack_align, sparc32_register_name,
+	sparc64_register_name, sparc_print_extra_frame_info,
+	sparclite_register_name, sparclet_register_name, 
+	sparc_push_return_address, sparc64_use_struct_convention, 
+	sparc32_store_struct_return, sparc64_store_struct_return, 
+	sparc32_register_virtual_type, sparc64_register_virtual_type, 
+	sparc32_register_size, sparc64_register_size, 
+	sparc32_register_byte, sparc64_register_byte, 
+	sparc_gdbarch_skip_prologue, sparc_convert_to_virtual, 
+	sparc_convert_to_raw, sparc_frame_init_saved_regs, 
+	sparc_frame_address, sparc_gdbarch_fix_call_dummy, 
+	sparc_coerce_float_to_double, sparc_call_dummy_address, 
+	sparc_y_regnum, sparc_reg_struct_has_addr, sparc_intreg_size,
+	sparc_return_value_on_stack): New functions supporting multi-arch.
+	(sparc_gdbarch_init): New function; initialize multi-arch.
+	(struct gdbarch_tdep): Define, use for private multi-arch data.
+	* config/sparc/tm-sparc.h: Move definitions around, enclose with
+	#ifdef GDB_MULTI_ARCH tests, provide some multi-arch alternate
+	definitions.  Add enums for register names, to help debugging gdb.
+	This header file must work for non-multi-arch and for multi-arch.
+	* config/sparc/tm-sp64.h: Add GDB_MULTI_ARCH configuration.  Also add
+	AT_ENTRY_POINT definitions for CALL_DUMMY, for non-multi-arch case.
+	Define GDB_MULTI_ARCH.
+	* config/sparc/tm-sparclet.h: Add GDB_MULTI_ARCH configuration.
+	Do not define GDB_MULTI_ARCH (bfd does not correctly identify target).
+	* config/sparc/tm-sparclite.h: Ditto.
+	* config/sparc/tm-sun4sol2.h: Define GDB_MULTI_ARCH.
+	* sparclet-rom.c (sparclet_regnames): Initialize explicitly, to
+	avoid using deprecated REGISTER_NAMES macro.
+	* Makefile.in: Let sparc-tdep.c depend on arch-utils.h.
+
 2000-05-08  Michael Snyder  <msnyder@seadog.cygnus.com>
 
 	* gdbarch.sh: Add FP0_REGNUM to list of multi-arched register numbers.
diff --git a/gdb/Makefile.in b/gdb/Makefile.in
index 5034977..0d33e74 100644
--- a/gdb/Makefile.in
+++ b/gdb/Makefile.in
@@ -1802,7 +1802,8 @@ sparc-nat.o: sparc-nat.c $(bfd_h) $(defs_h) $(inferior_h) $(gdbcore_h) \
 	target.h
 
 sparc-tdep.o: sparc-tdep.c $(floatformat_h) $(defs_h) $(gdbcore_h) \
-	$(inferior_h) objfiles.h symfile.h target.h gdb_string.h
+	$(inferior_h) objfiles.h symfile.h target.h gdb_string.h \
+	$(arch_utils_h)
 
 sparcl-tdep.o: sparcl-tdep.c $(defs_h) $(gdbcore_h) target.h
 
diff --git a/gdb/config/sparc/tm-sp64.h b/gdb/config/sparc/tm-sp64.h
index dbdf510..378212d 100644
--- a/gdb/config/sparc/tm-sp64.h
+++ b/gdb/config/sparc/tm-sp64.h
@@ -22,9 +22,13 @@
    Foundation, Inc., 59 Temple Place - Suite 330,
    Boston, MA 02111-1307, USA.  */
 
-#define GDB_TARGET_IS_SPARC64
+#define GDB_MULTI_ARCH 2
 
-struct value;
+#ifndef GDB_TARGET_IS_SPARC64
+#define GDB_TARGET_IS_SPARC64 1
+#endif
+
+#include "sparc/tm-sparc.h"
 
 /* Eeeew. Ok, we have to assume (for now) that the processor really is
    in sparc64 mode. While this is the same instruction sequence as
@@ -70,6 +74,57 @@ struct value;
    nop
  */
 
+#if !defined (GDB_MULTI_ARCH) || (GDB_MULTI_ARCH == 0)
+/*
+ * The following defines must go away for MULTI_ARCH.
+ */
+
+#ifndef DO_CALL_DUMMY_ON_STACK
+
+/*
+ * These defines will suffice for the AT_ENTRY_POINT call dummy method.
+ */
+
+#undef  CALL_DUMMY
+#define CALL_DUMMY {0}
+#undef  CALL_DUMMY_LENGTH
+#define CALL_DUMMY_LENGTH 0
+#undef  CALL_DUMMY_CALL_OFFSET
+#define CALL_DUMMY_CALL_OFFSET 0
+#undef  CALL_DUMMY_START_OFFSET
+#define CALL_DUMMY_START_OFFSET 0
+#undef  CALL_DUMMY_BREAKPOINT_OFFSET
+#define CALL_DUMMY_BREAKPOINT_OFFSET 0
+#undef  CALL_DUMMY_BREAKPOINT_OFFSET_P
+#define CALL_DUMMY_BREAKPOINT_OFFSET_P 1
+#undef  CALL_DUMMY_LOCATION 
+#define CALL_DUMMY_LOCATION AT_ENTRY_POINT
+#undef  CALL_DUMMY_STACK_ADJUST
+#define CALL_DUMMY_STACK_ADJUST 128
+#undef  SIZEOF_CALL_DUMMY_WORDS
+#define SIZEOF_CALL_DUMMY_WORDS 0
+#undef  CALL_DUMMY_ADDRESS
+#define CALL_DUMMY_ADDRESS() entry_point_address()
+#undef  FIX_CALL_DUMMY
+#define FIX_CALL_DUMMY(DUMMYNAME, PC, FUN, NARGS, ARGS, TYPE, GCC_P) 
+#undef  PUSH_RETURN_ADDRESS
+#define PUSH_RETURN_ADDRESS(PC, SP) sparc_at_entry_push_return_address (PC, SP)
+extern CORE_ADDR 
+sparc_at_entry_push_return_address (CORE_ADDR pc, CORE_ADDR sp);
+
+#undef  STORE_STRUCT_RETURN
+#define STORE_STRUCT_RETURN(ADDR, SP) \
+     sparc_at_entry_store_struct_return (ADDR, SP)
+extern void 
+sparc_at_entry_store_struct_return (CORE_ADDR addr, CORE_ADDR sp);
+
+
+#else
+/*
+ * Old call dummy method, with CALL_DUMMY on the stack.
+ */
+
+#undef  CALL_DUMMY
 #define CALL_DUMMY {		 0x9de3bec0fd3fa7f7LL, 0xf93fa7eff53fa7e7LL,\
 				 0xf13fa7dfed3fa7d7LL, 0xe93fa7cfe53fa7c7LL,\
 				 0xe13fa7bfdd3fa7b7LL, 0xd93fa7afd53fa7a7LL,\
@@ -86,17 +141,83 @@ struct value;
 
 /* 128 is to reserve space to write the %i/%l registers that will be restored
    when we resume. */
+#undef  CALL_DUMMY_STACK_ADJUST
 #define CALL_DUMMY_STACK_ADJUST 128
 
+/* Size of the call dummy in bytes. */
+#undef  CALL_DUMMY_LENGTH
 #define CALL_DUMMY_LENGTH 192
 
+/* Offset within CALL_DUMMY of the 'call' instruction. */
+#undef  CALL_DUMMY_START_OFFSET
 #define CALL_DUMMY_START_OFFSET 148
 
+/* Offset within CALL_DUMMY of the 'call' instruction. */
+#undef  CALL_DUMMY_CALL_OFFSET
 #define CALL_DUMMY_CALL_OFFSET (CALL_DUMMY_START_OFFSET + (5 * 4))
 
+/* Offset within CALL_DUMMY of the 'ta 1' instruction. */
+#undef  CALL_DUMMY_BREAKPOINT_OFFSET
 #define CALL_DUMMY_BREAKPOINT_OFFSET (CALL_DUMMY_START_OFFSET + (8 * 4))
 
-#include "sparc/tm-sparc.h"
+/* Let's GDB know that it can make a call_dummy breakpoint.  */
+#undef  CALL_DUMMY_BREAKPOINT_OFFSET_P
+#define CALL_DUMMY_BREAKPOINT_OFFSET_P 1
+
+/* Call dummy will be located on the stack.  */
+#undef  CALL_DUMMY_LOCATION
+#define CALL_DUMMY_LOCATION ON_STACK
+
+/* Insert the function address into the call dummy.  */
+#undef  FIX_CALL_DUMMY
+#define FIX_CALL_DUMMY(dummyname, pc, fun, nargs, args, type, gcc_p) \
+ sparc_fix_call_dummy (dummyname, pc, fun, type, gcc_p)
+void sparc_fix_call_dummy PARAMS ((char *dummy, CORE_ADDR pc, CORE_ADDR fun,
+                                   struct type * value_type, int using_gcc));
+
+
+/* The remainder of these will accept the default definition.  */
+#undef  SIZEOF_CALL_DUMMY_WORDS
+#undef  PUSH_RETURN_ADDRESS
+#undef  CALL_DUMMY_ADDRESS
+#undef  STORE_STRUCT_RETURN
+
+#endif
+
+/* Does the specified function use the "struct returning" convention
+   or the "value returning" convention?  The "value returning" convention
+   almost invariably returns the entire value in registers.  The
+   "struct returning" convention often returns the entire value in
+   memory, and passes a pointer (out of or into the function) saying
+   where the value (is or should go).
+
+   Since this sometimes depends on whether it was compiled with GCC,
+   this is also an argument.  This is used in call_function to build a
+   stack, and in value_being_returned to print return values. 
+
+   On Sparc64, we only pass pointers to structs if they're larger then
+   32 bytes. Otherwise they're stored in %o0-%o3 (floating-point
+   values go into %fp0-%fp3).  */
+
+#undef  USE_STRUCT_CONVENTION
+#define USE_STRUCT_CONVENTION(gcc_p, type) (TYPE_LENGTH (type) > 32)
+
+CORE_ADDR sparc64_push_arguments PARAMS ((int, 
+					  struct value **, 
+					  CORE_ADDR, 
+					  int,
+					  CORE_ADDR));
+#undef PUSH_ARGUMENTS
+#define PUSH_ARGUMENTS(A,B,C,D,E) \
+     (sparc64_push_arguments ((A), (B), (C), (D), (E)))
+
+/* Store the address of the place in which to copy the structure the
+   subroutine will return.  This is called from call_function. */
+/* FIXME: V9 uses %o0 for this.  */
+
+#undef  STORE_STRUCT_RETURN
+#define STORE_STRUCT_RETURN(ADDR, SP) \
+  { target_write_memory ((SP)+(16*8), (char *)&(ADDR), 8); }
 
 /* Stack must be aligned on 128-bit boundaries when synthesizing
    function calls. */
@@ -104,11 +225,6 @@ struct value;
 #undef  STACK_ALIGN
 #define STACK_ALIGN(ADDR) (((ADDR) + 15 ) & -16)
 
-/* Number of machine registers.  */
-
-#undef  NUM_REGS
-#define NUM_REGS 125
-
 /* Initializer for an array of names of registers.
    There should be NUM_REGS strings in this initializer.  */
 /* Some of these registers are only accessible from priviledged mode.
@@ -148,6 +264,25 @@ struct value;
   "icc", "xcc", "fcc0", "fcc1", "fcc2", "fcc3"			\
 }
 
+#undef REG_STRUCT_HAS_ADDR
+#define REG_STRUCT_HAS_ADDR(gcc_p,type) (TYPE_LENGTH (type) > 32)
+
+extern CORE_ADDR sparc64_read_sp ();
+extern CORE_ADDR sparc64_read_fp ();
+extern void sparc64_write_sp PARAMS ((CORE_ADDR));
+extern void sparc64_write_fp PARAMS ((CORE_ADDR));
+
+#define TARGET_READ_SP() (sparc64_read_sp ())
+#define TARGET_READ_FP() (sparc64_read_fp ())
+#define TARGET_WRITE_SP(X) (sparc64_write_sp (X))
+#define TARGET_WRITE_FP(X) (sparc64_write_fp (X))
+
+#undef EXTRACT_RETURN_VALUE
+#define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
+     sp64_extract_return_value(TYPE, REGBUF, VALBUF, 0)
+extern void
+sp64_extract_return_value PARAMS ((struct type *, char[], char *, int));
+
 /* Register numbers of various important registers.
    Note that some of these values are "real" register numbers,
    and correspond to the general registers of the machine,
@@ -155,7 +290,8 @@ struct value;
    to be actual register numbers as far as the user is concerned
    but do serve to get the desired values when passed to read_register.  */
 
-#if 0				/* defined in tm-sparc.h, replicated for doc purposes */
+#if 0				/* defined in tm-sparc.h, replicated
+				   for doc purposes */
 #define	G0_REGNUM 0		/* %g0 */
 #define	G1_REGNUM 1		/* %g1 */
 #define O0_REGNUM 8		/* %o0 */
@@ -172,7 +308,7 @@ struct value;
 #define	FP0_REGNUM 32		/* Floating point register 0 */
 #endif
 
-#define FP_MAX_REGNUM 80	/* 1 + last fp reg number */
+/*#define FP_MAX_REGNUM 80*/	/* 1 + last fp reg number */
 
 /* #undef v8 misc. regs */
 
@@ -187,7 +323,8 @@ struct value;
 
 /* v9 misc. and priv. regs */
 
-#define C0_REGNUM FP_MAX_REGNUM	/* Start of control registers */
+#define C0_REGNUM 80			/* Start of control registers */
+
 #define PC_REGNUM (C0_REGNUM + 0)	/* Current PC */
 #define NPC_REGNUM (C0_REGNUM + 1)	/* Next PC */
 #define CCR_REGNUM (C0_REGNUM + 2)	/* Condition Code Register (%xcc,%icc) */
@@ -220,6 +357,11 @@ struct value;
 #define FCC2_REGNUM (C0_REGNUM + 43)	/* fp cc reg 2 */
 #define FCC3_REGNUM (C0_REGNUM + 44)	/* fp cc reg 3 */
 
+/* Number of machine registers.  */
+
+#undef  NUM_REGS
+#define NUM_REGS 125
+
 /* Total amount of space needed to store our copies of the machine's
    register state, the array `registers'.
    Some of the registers aren't 64 bits, but it's a lot simpler just to assume
@@ -291,40 +433,12 @@ struct value;
 #undef TARGET_LONG_LONG_BIT
 #define TARGET_LONG_LONG_BIT 64
 
-/* Does the specified function use the "struct returning" convention
-   or the "value returning" convention?  The "value returning" convention
-   almost invariably returns the entire value in registers.  The
-   "struct returning" convention often returns the entire value in
-   memory, and passes a pointer (out of or into the function) saying
-   where the value (is or should go).
-
-   Since this sometimes depends on whether it was compiled with GCC,
-   this is also an argument.  This is used in call_function to build a
-   stack, and in value_being_returned to print return values. 
-
-   On Sparc64, we only pass pointers to structs if they're larger then
-   32 bytes. Otherwise they're stored in %o0-%o3 (floating-point
-   values go into %fp0-%fp3).  */
-
-
-#undef  USE_STRUCT_CONVENTION
-#define USE_STRUCT_CONVENTION(gcc_p, type) (TYPE_LENGTH (type) > 32)
-
-#undef REG_STRUCT_HAS_ADDR
-#define REG_STRUCT_HAS_ADDR(gcc_p,type) (TYPE_LENGTH (type) > 32)
-
-/* Store the address of the place in which to copy the structure the
-   subroutine will return.  This is called from call_function. */
-/* FIXME: V9 uses %o0 for this.  */
-
-#undef  STORE_STRUCT_RETURN
-#define STORE_STRUCT_RETURN(ADDR, SP) \
-  { target_write_memory ((SP)+(16*8), (char *)&(ADDR), 8); }
-
 /* Return number of bytes at start of arglist that are not really args.  */
 
 #undef  FRAME_ARGS_SKIP
 #define FRAME_ARGS_SKIP 136
+
+#endif /* GDB_MULTI_ARCH */
 
 /* Offsets into jmp_buf.
    FIXME: This was borrowed from the v8 stuff and will probably have to change
@@ -342,36 +456,18 @@ struct value;
 #define JB_O0 7
 #define JB_WBCNT 8
 
-/* Figure out where the longjmp will land.  We expect that we have just entered
-   longjmp and haven't yet setup the stack frame, so the args are still in the
-   output regs.  %o0 (O0_REGNUM) points at the jmp_buf structure from which we
-   extract the pc (JB_PC) that we will land at.  The pc is copied into ADDR.
-   This routine returns true on success */
+/* Figure out where the longjmp will land.  We expect that we have
+   just entered longjmp and haven't yet setup the stack frame, so the
+   args are still in the output regs.  %o0 (O0_REGNUM) points at the
+   jmp_buf structure from which we extract the pc (JB_PC) that we will
+   land at.  The pc is copied into ADDR.  This routine returns true on
+   success */
 
 extern int
 get_longjmp_target PARAMS ((CORE_ADDR *));
 
 #define GET_LONGJMP_TARGET(ADDR) get_longjmp_target(ADDR)
 
-extern CORE_ADDR sparc64_read_sp ();
-extern CORE_ADDR sparc64_read_fp ();
-extern void sparc64_write_sp PARAMS ((CORE_ADDR));
-extern void sparc64_write_fp PARAMS ((CORE_ADDR));
-
-#define TARGET_READ_SP() (sparc64_read_sp ())
-#define TARGET_READ_FP() (sparc64_read_fp ())
-#define TARGET_WRITE_SP(X) (sparc64_write_sp (X))
-#define TARGET_WRITE_FP(X) (sparc64_write_fp (X))
-
 #undef TM_PRINT_INSN_MACH
 #define TM_PRINT_INSN_MACH bfd_mach_sparc_v9a
 
-CORE_ADDR sp64_push_arguments PARAMS ((int, struct value **, CORE_ADDR, unsigned char, CORE_ADDR));
-#undef PUSH_ARGUMENTS
-#define PUSH_ARGUMENTS(A,B,C,D,E) (sp64_push_arguments ((A), (B), (C), (D), (E)))
-
-#undef EXTRACT_RETURN_VALUE
-#define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
-  sparc64_extract_return_value(TYPE, REGBUF, VALBUF, 0)
-extern void
-sparc64_extract_return_value PARAMS ((struct type *, char[], char *, int));
diff --git a/gdb/config/sparc/tm-sparc.h b/gdb/config/sparc/tm-sparc.h
index 29cf746..63148ce 100644
--- a/gdb/config/sparc/tm-sparc.h
+++ b/gdb/config/sparc/tm-sparc.h
@@ -21,103 +21,148 @@
    Foundation, Inc., 59 Temple Place - Suite 330,
    Boston, MA 02111-1307, USA.  */
 
-struct frame_info;
 struct type;
 struct value;
+struct frame_info;
 
-#define TARGET_BYTE_ORDER BIG_ENDIAN
-
-/* Floating point is IEEE compatible.  */
-#define IEEE_FLOAT (1)
-
-/* If an argument is declared "register", Sun cc will keep it in a register,
-   never saving it onto the stack.  So we better not believe the "p" symbol
-   descriptor stab.  */
-
-#define USE_REGISTER_NOT_ARG
-
-/* When passing a structure to a function, Sun cc passes the address
-   not the structure itself.  It (under SunOS4) creates two symbols,
-   which we need to combine to a LOC_REGPARM.  Gcc version two (as of
-   1.92) behaves like sun cc.  REG_STRUCT_HAS_ADDR is smart enough to
-   distinguish between Sun cc, gcc version 1 and gcc version 2.  */
-
-#define REG_STRUCT_HAS_ADDR(gcc_p,type) (gcc_p != 1)
-
-/* Sun /bin/cc gets this right as of SunOS 4.1.x.  We need to define
-   BELIEVE_PCC_PROMOTION to get this right now that the code which
-   detects gcc2_compiled. is broken.  This loses for SunOS 4.0.x and
-   earlier.  */
+/*
+ * The following enums are purely for the convenience of the GDB 
+ * developer, when debugging GDB.
+ */
 
-#define BELIEVE_PCC_PROMOTION 1
+enum {	/* Sparc general registers, for all sparc versions.  */
+  G0_REGNUM, G1_REGNUM, G2_REGNUM, G3_REGNUM, 
+  G4_REGNUM, G5_REGNUM, G6_REGNUM, G7_REGNUM, 
+  O0_REGNUM, O1_REGNUM, O2_REGNUM, O3_REGNUM, 
+  O4_REGNUM, O5_REGNUM, O6_REGNUM, O7_REGNUM,
+  L0_REGNUM, L1_REGNUM, L2_REGNUM, L3_REGNUM, 
+  L4_REGNUM, L5_REGNUM, L6_REGNUM, L7_REGNUM, 
+  I0_REGNUM, I1_REGNUM, I2_REGNUM, I3_REGNUM, 
+  I4_REGNUM, I5_REGNUM, I6_REGNUM, I7_REGNUM,
+  FP0_REGNUM 		/* Floating point register 0 */
+};
+
+enum {	/* Sparc general registers, alternate names.  */
+  R0_REGNUM,  R1_REGNUM,  R2_REGNUM,  R3_REGNUM, 
+  R4_REGNUM,  R5_REGNUM,  R6_REGNUM,  R7_REGNUM, 
+  R8_REGNUM,  R9_REGNUM,  R10_REGNUM, R11_REGNUM, 
+  R12_REGNUM, R13_REGNUM, R14_REGNUM, R15_REGNUM, 
+  R16_REGNUM, R17_REGNUM, R18_REGNUM, R19_REGNUM, 
+  R20_REGNUM, R21_REGNUM, R22_REGNUM, R23_REGNUM, 
+  R24_REGNUM, R25_REGNUM, R26_REGNUM, R27_REGNUM, 
+  R28_REGNUM, R29_REGNUM, R30_REGNUM, R31_REGNUM
+};
+
+enum {			/* Sparc32 control registers.  */
+  PS_REGNUM  = 65, 	/* PC, NPC, and Y are omitted because */
+  WIM_REGNUM = 66,	/* they have different values depending on */
+  TBR_REGNUM = 67,	/* 32-bit / 64-bit mode.  */
+  FPS_REGNUM = 70,
+  CPS_REGNUM = 71
+};
+
+/* v9 misc. and priv. regs */
+
+/* Note: specifying values explicitly for documentation purposes.  */
+enum {	/* Sparc64 control registers, excluding Y, PC, and NPC.  */
+  CCR_REGNUM = 82,		/* Condition Code Register (%xcc,%icc) */
+  FSR_REGNUM = 83,		/* Floating Point State */
+  FPRS_REGNUM = 84,		/* Floating Point Registers State */
+  ASI_REGNUM = 86,		/* Alternate Space Identifier */
+  VER_REGNUM = 87,		/* Version register */
+  TICK_REGNUM = 88,		/* Tick register */
+  PIL_REGNUM = 89, 		/* Processor Interrupt Level */
+  PSTATE_REGNUM = 90,		/* Processor State */
+  TSTATE_REGNUM = 91,		/* Trap State */
+  TBA_REGNUM = 92,		/* Trap Base Address */
+  TL_REGNUM = 93,		/* Trap Level */
+  TT_REGNUM = 94,		/* Trap Type */
+  TPC_REGNUM = 95,		/* Trap pc */
+  TNPC_REGNUM = 96,		/* Trap npc */
+  WSTATE_REGNUM = 97,		/* Window State */
+  CWP_REGNUM = 98,		/* Current Window Pointer */
+  CANSAVE_REGNUM = 99,		/* Savable Windows */
+  CANRESTORE_REGNUM = 100,	/* Restorable Windows */
+  CLEANWIN_REGNUM = 101,	/* Clean Windows */
+  OTHERWIN_REGNUM = 102,	/* Other Windows */
+  ASR16_REGNUM = 103,		/* Ancillary State Registers */
+  ASR17_REGNUM = 104,
+  ASR18_REGNUM = 105,
+  ASR19_REGNUM = 106,
+  ASR20_REGNUM = 107,
+  ASR21_REGNUM = 108,
+  ASR22_REGNUM = 109,
+  ASR23_REGNUM = 110,
+  ASR24_REGNUM = 111,
+  ASR25_REGNUM = 112,
+  ASR26_REGNUM = 113,
+  ASR27_REGNUM = 114,
+  ASR28_REGNUM = 115,
+  ASR29_REGNUM = 116,
+  ASR30_REGNUM = 117,
+  ASR31_REGNUM = 118,
+  ICC_REGNUM   = 119,		/* 32 bit condition codes */
+  XCC_REGNUM   = 120,		/* 64 bit condition codes */
+  FCC0_REGNUM  = 121,		/* fp cc reg 0 */
+  FCC1_REGNUM  = 122,		/* fp cc reg 1 */
+  FCC2_REGNUM  = 123,		/* fp cc reg 2 */
+  FCC3_REGNUM  = 124		/* fp cc reg 3 */
+};
 
-/* For acc, there's no need to correct LBRAC entries by guessing how
-   they should work.  In fact, this is harmful because the LBRAC
-   entries now all appear at the end of the function, not intermixed
-   with the SLINE entries.  n_opt_found detects acc for Solaris binaries;
-   function_stab_type detects acc for SunOS4 binaries.
+/*
+ * Make sparc target multi-archable: April 2000
+ */
 
-   For binary from SunOS4 /bin/cc, need to correct LBRAC's.
+#if defined (GDB_MULTI_ARCH) && (GDB_MULTI_ARCH > 0)
+
+/* Multi-arch definition of TARGET_IS_SPARC64, TARGET_ELF64 */
+#undef  GDB_TARGET_IS_SPARC64
+#define GDB_TARGET_IS_SPARC64 \
+     (sparc_intreg_size () == 8)
+#undef  TARGET_ELF64
+#define TARGET_ELF64 \
+     (sparc_intreg_size () == 8)
+extern int sparc_intreg_size (void);
+#else
+
+/* Non-multi-arch: if it isn't defined, define it to zero.  */
+#ifndef GDB_TARGET_IS_SPARC64
+#define GDB_TARGET_IS_SPARC64 0
+#endif
+#ifndef TARGET_ELF64
+#define TARGET_ELF64 0
+#endif
+#endif
 
-   For gcc, like acc, don't correct.  */
+#if !defined (GDB_MULTI_ARCH) || (GDB_MULTI_ARCH == 0)
+/*
+ * The following defines must go away for MULTI_ARCH
+ */
 
-#define	SUN_FIXED_LBRAC_BUG \
-  (n_opt_found \
-   || function_stab_type == N_STSYM \
-   || function_stab_type == N_GSYM \
-   || processing_gcc_compilation)
+/* Initializer for an array of names of registers.
+   There should be NUM_REGS strings in this initializer.  */
 
-/* Do variables in the debug stabs occur after the N_LBRAC or before it?
-   acc: after, gcc: before, SunOS4 /bin/cc: before.  */
+#define REGISTER_NAMES  \
+{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",		\
+  "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",		\
+  "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",		\
+  "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",		\
+								\
+  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",		\
+  "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",		\
+  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",	\
+  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",	\
+                                                                \
+  "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr" 	\
+}
 
-#define VARIABLES_INSIDE_BLOCK(desc, gcc_p) \
-  (!(gcc_p) \
-   && (n_opt_found \
-       || function_stab_type == N_STSYM \
-       || function_stab_type == N_GSYM))
+#define TARGET_BYTE_ORDER BIG_ENDIAN
 
 /* Offset from address of function to start of its code.
    Zero on most machines.  */
 
 #define FUNCTION_START_OFFSET 0
 
-/* Advance PC across any function entry prologue instructions
-   to reach some "real" code.  SKIP_PROLOGUE_FRAMELESS_P advances
-   the PC past some of the prologue, but stops as soon as it
-   knows that the function has a frame.  Its result is equal
-   to its input PC if the function is frameless, unequal otherwise.  */
-
-#define SKIP_PROLOGUE(pc) (sparc_skip_prologue (pc, 0))
-#define SKIP_PROLOGUE_FRAMELESS_P(pc) (sparc_skip_prologue (pc, 1))
-extern CORE_ADDR sparc_skip_prologue PARAMS ((CORE_ADDR, int));
-
-/* Immediately after a function call, return the saved pc.
-   Can't go through the frames for this because on some machines
-   the new frame is not set up until the new function executes
-   some instructions.  */
-
-/* On the Sun 4 under SunOS, the compile will leave a fake insn which
-   encodes the structure size being returned.  If we detect such
-   a fake insn, step past it.  */
-
-#define PC_ADJUST(pc) sparc_pc_adjust(pc)
-extern CORE_ADDR sparc_pc_adjust PARAMS ((CORE_ADDR));
-
-#define SAVED_PC_AFTER_CALL(frame) PC_ADJUST (read_register (RP_REGNUM))
-
-/* Stack grows downward.  */
-
-#define INNER_THAN(lhs,rhs) ((lhs) < (rhs))
-
-/* Stack must be aligned on 64-bit boundaries when synthesizing
-   function calls. */
-
-#define STACK_ALIGN(ADDR) (((ADDR) + 7) & -8)
-
-/* Sequence of bytes for breakpoint instruction (ta 1). */
-
-#define BREAKPOINT {0x91, 0xd0, 0x20, 0x01}
-
 /* Amount PC must be decremented by after a breakpoint.
    This is often the number of bytes in BREAKPOINT
    but not always.  */
@@ -134,91 +179,48 @@ extern CORE_ADDR sparc_pc_adjust PARAMS ((CORE_ADDR));
 
 #define NUM_REGS 72
 
-/* Initializer for an array of names of registers.
-   There should be NUM_REGS strings in this initializer.  */
-
-#define REGISTER_NAMES  \
-{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",	\
-  "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",	\
-  "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",	\
-  "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",	\
-								\
-  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",	\
-  "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",	\
-  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",	\
-  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",	\
-                                                                \
-  "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr" }
-
-/* Register numbers of various important registers.
-   Note that some of these values are "real" register numbers,
-   and correspond to the general registers of the machine,
-   and some are "phony" register numbers which are too large
-   to be actual register numbers as far as the user is concerned
-   but do serve to get the desired values when passed to read_register.  */
-
-#define	G0_REGNUM 0		/* %g0 */
-#define	G1_REGNUM 1		/* %g1 */
-#define O0_REGNUM 8		/* %o0 */
 #define	SP_REGNUM 14		/* Contains address of top of stack, \
 				   which is also the bottom of the frame.  */
-#define	RP_REGNUM 15		/* Contains return address value, *before* \
-				   any windows get switched.  */
-#define	O7_REGNUM 15		/* Last local reg not saved on stack frame */
-#define	L0_REGNUM 16		/* First local reg that's saved on stack frame
-				   rather than in machine registers */
-#define	I0_REGNUM 24		/* %i0 */
 #define	FP_REGNUM 30		/* Contains address of executing stack frame */
-#define	I7_REGNUM 31		/* Last local reg saved on stack frame */
+
 #define	FP0_REGNUM 32		/* Floating point register 0 */
+
 #define	Y_REGNUM 64		/* Temp register for multiplication, etc.  */
-#define	PS_REGNUM 65		/* Contains processor status */
-#define PS_FLAG_CARRY 0x100000	/* Carry bit in PS */
-#define	WIM_REGNUM 66		/* Window Invalid Mask (not really supported) */
-#define	TBR_REGNUM 67		/* Trap Base Register (not really supported) */
+
 #define	PC_REGNUM 68		/* Contains program counter */
+
 #define	NPC_REGNUM 69		/* Contains next PC */
-#define	FPS_REGNUM 70		/* Floating point status register */
-#define	CPS_REGNUM 71		/* Coprocessor status register */
+
 
 /* Total amount of space needed to store our copies of the machine's
    register state, the array `registers'.  On the sparc, `registers'
    contains the ins and locals, even though they are saved on the
    stack rather than with the other registers, and this causes hair
-   and confusion in places like pop_frame.  It might be
-   better to remove the ins and locals from `registers', make sure
-   that get_saved_register can get them from the stack (even in the
+   and confusion in places like pop_frame.  It might be better to
+   remove the ins and locals from `registers', make sure that
+   get_saved_register can get them from the stack (even in the
    innermost frame), and make this the way to access them.  For the
-   frame pointer we would do that via TARGET_READ_FP.  On the other hand,
-   that is likely to be confusing or worse for flat frames.  */
+   frame pointer we would do that via TARGET_READ_FP.  On the other
+   hand, that is likely to be confusing or worse for flat frames.  */
 
 #define REGISTER_BYTES (32*4+32*4+8*4)
 
 /* Index within `registers' of the first byte of the space for
    register N.  */
-/* ?? */
-#define REGISTER_BYTE(N)  ((N)*4)
 
-/* We need to override GET_SAVED_REGISTER so that we can deal with the way
-   outs change into ins in different frames.  HAVE_REGISTER_WINDOWS can't
-   deal with this case and also handle flat frames at the same time.  */
-
-struct frame_info;
-void sparc_get_saved_register PARAMS ((char *raw_buffer, int *optimized, CORE_ADDR * addrp, struct frame_info * frame, int regnum, enum lval_type * lvalp));
-#define GET_SAVED_REGISTER(raw_buffer, optimized, addrp, frame, regnum, lval) \
-      sparc_get_saved_register (raw_buffer, optimized, addrp, frame, regnum, lval)
+#define REGISTER_BYTE(N)  ((N)*4)
 
-/* Number of bytes of storage in the actual machine representation
-   for register N.  */
+/* Number of bytes of storage in the actual machine representation for
+   register N.  */
 
-/* On the SPARC, all regs are 4 bytes.  */
+/* On the SPARC, all regs are 4 bytes (except Sparc64, where they're 8).  */
 
 #define REGISTER_RAW_SIZE(N) (4)
 
 /* Number of bytes of storage in the program's representation
    for register N.  */
 
-/* On the SPARC, all regs are 4 bytes.  */
+/* On the SPARC, all regs are 4 bytes (except Sparc64, where they're 8).  */
 
 #define REGISTER_VIRTUAL_SIZE(N) (4)
 
@@ -234,36 +236,40 @@ void sparc_get_saved_register PARAMS ((char *raw_buffer, int *optimized, CORE_AD
    of data in register N.  */
 
 #define REGISTER_VIRTUAL_TYPE(N) \
- ((N) < 32 ? builtin_type_int : (N) < 64 ? builtin_type_float : \
-  builtin_type_int)
+     ((N) < 32 ? builtin_type_int : (N) < 64 ? builtin_type_float : \
+      builtin_type_int)
 
-/* Writing to %g0 is a noop (not an error or exception or anything like
-   that, however).  */
+/* Sun /bin/cc gets this right as of SunOS 4.1.x.  We need to define
+   BELIEVE_PCC_PROMOTION to get this right now that the code which
+   detects gcc2_compiled. is broken.  This loses for SunOS 4.0.x and
+   earlier.  */
 
-#define CANNOT_STORE_REGISTER(regno) ((regno) == G0_REGNUM)
+#define BELIEVE_PCC_PROMOTION 1
 
-/* Store the address of the place in which to copy the structure the
-   subroutine will return.  This is called from call_function_by_hand. 
-   The ultimate mystery is, tho, what is the value "16"?  */
+/* Advance PC across any function entry prologue instructions
+   to reach some "real" code.  SKIP_PROLOGUE_FRAMELESS_P advances
+   the PC past some of the prologue, but stops as soon as it
+   knows that the function has a frame.  Its result is equal
+   to its input PC if the function is frameless, unequal otherwise.  */
 
-#define STORE_STRUCT_RETURN(ADDR, SP) \
-  { char val[4]; \
-    store_unsigned_integer (val, 4, (ADDR)); \
-    write_memory ((SP)+(16*4), val, 4); }
+#define SKIP_PROLOGUE(PC) sparc_skip_prologue (PC, 0)
 
-/* Extract from an array REGBUF containing the (raw) register state
-   a function return value of type TYPE, and copy that, in virtual format,
-   into VALBUF.  */
+/* Immediately after a function call, return the saved pc.
+   Can't go through the frames for this because on some machines
+   the new frame is not set up until the new function executes
+   some instructions.  */
 
-#define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
-  sparc_extract_return_value(TYPE, REGBUF, VALBUF)
-extern void
-sparc_extract_return_value PARAMS ((struct type *, char[], char *));
+#define SAVED_PC_AFTER_CALL(FRAME) PC_ADJUST (read_register (RP_REGNUM))
+
+/* Stack grows downward.  */
+
+#define INNER_THAN(LHS,RHS) ((LHS) < (RHS))
+
+/* Write into appropriate registers a function return value of type
+   TYPE, given in virtual format.  */
 
-/* Write into appropriate registers a function return value
-   of type TYPE, given in virtual format.  */
-#define STORE_RETURN_VALUE(TYPE,VALBUF) \
-  sparc_store_return_value(TYPE, VALBUF)
+#define STORE_RETURN_VALUE(TYPE, VALBUF) \
+     sparc_store_return_value (TYPE, VALBUF)
 extern void sparc_store_return_value PARAMS ((struct type *, char *));
 
 /* Extract from an array REGBUF containing the (raw) register state
@@ -271,11 +277,146 @@ extern void sparc_store_return_value PARAMS ((struct type *, char *));
    as a CORE_ADDR (or an expression that can be used as one).  */
 
 #define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
-  (sparc_extract_struct_value_address (REGBUF))
+     sparc_extract_struct_value_address (REGBUF)
 
 extern CORE_ADDR
-  sparc_extract_struct_value_address PARAMS ((char[REGISTER_BYTES]));
-
+sparc_extract_struct_value_address PARAMS ((char *));
+
+/* If the current gcc for for this target does not produce correct
+   debugging information for float parameters, both prototyped and
+   unprototyped, then define this macro.  This forces gdb to always
+   assume that floats are passed as doubles and then converted in the
+   callee. */
+
+#define COERCE_FLOAT_TO_DOUBLE(FORMAL, ACTUAL) (1)
+
+/* Stack must be aligned on 64-bit boundaries when synthesizing
+   function calls (128-bit for sparc64).  */
+
+#define STACK_ALIGN(ADDR) sparc32_stack_align (ADDR)
+extern CORE_ADDR sparc32_stack_align (CORE_ADDR addr);
+
+/* Floating point is IEEE compatible.  */
+#define IEEE_FLOAT (1)
+
+/* The Sparc returns long doubles on the stack.  */
+
+#define RETURN_VALUE_ON_STACK(TYPE) \
+  (TYPE_CODE(TYPE) == TYPE_CODE_FLT \
+   && TYPE_LENGTH(TYPE) > 8)
+
+/* When passing a structure to a function, Sun cc passes the address
+   not the structure itself.  It (under SunOS4) creates two symbols,
+   which we need to combine to a LOC_REGPARM.  Gcc version two (as of
+   1.92) behaves like sun cc.  REG_STRUCT_HAS_ADDR is smart enough to
+   distinguish between Sun cc, gcc version 1 and gcc version 2.  */
+
+#define REG_STRUCT_HAS_ADDR(GCC_P, TYPE) \
+     sparc_reg_struct_has_addr (GCC_P, TYPE)
+extern int sparc_reg_struct_has_addr (int, struct type *);
+
+#endif /* GDB_MULTI_ARCH */
+
+#if defined (GDB_MULTI_ARCH) && (GDB_MULTI_ARCH > 0)
+/*
+ * The following defines should ONLY appear for MULTI_ARCH.
+ */
+
+/* Multi-arch the nPC and Y registers.  */
+#define Y_REGNUM              (sparc_y_regnum ())
+extern int sparc_npc_regnum (void);
+extern int sparc_y_regnum (void);
+
+#endif /* GDB_MULTI_ARCH */
+
+/* On the Sun 4 under SunOS, the compile will leave a fake insn which
+   encodes the structure size being returned.  If we detect such
+   a fake insn, step past it.  */
+
+#define PC_ADJUST(PC) sparc_pc_adjust (PC)
+extern CORE_ADDR sparc_pc_adjust PARAMS ((CORE_ADDR));
+
+/* Advance PC across any function entry prologue instructions to reach
+   some "real" code.  SKIP_PROLOGUE_FRAMELESS_P advances the PC past
+   some of the prologue, but stops as soon as it knows that the
+   function has a frame.  Its result is equal to its input PC if the
+   function is frameless, unequal otherwise.  */
+
+#define SKIP_PROLOGUE_FRAMELESS_P(PC) sparc_skip_prologue (PC, 1)
+extern CORE_ADDR sparc_skip_prologue PARAMS ((CORE_ADDR, int));
+
+/* If an argument is declared "register", Sun cc will keep it in a register,
+   never saving it onto the stack.  So we better not believe the "p" symbol
+   descriptor stab.  */
+
+#define USE_REGISTER_NOT_ARG
+
+/* For acc, there's no need to correct LBRAC entries by guessing how
+   they should work.  In fact, this is harmful because the LBRAC
+   entries now all appear at the end of the function, not intermixed
+   with the SLINE entries.  n_opt_found detects acc for Solaris binaries;
+   function_stab_type detects acc for SunOS4 binaries.
+
+   For binary from SunOS4 /bin/cc, need to correct LBRAC's.
+
+   For gcc, like acc, don't correct.  */
+
+#define	SUN_FIXED_LBRAC_BUG \
+  (n_opt_found \
+   || function_stab_type == N_STSYM \
+   || function_stab_type == N_GSYM \
+   || processing_gcc_compilation)
+
+/* Do variables in the debug stabs occur after the N_LBRAC or before it?
+   acc: after, gcc: before, SunOS4 /bin/cc: before.  */
+
+#define VARIABLES_INSIDE_BLOCK(desc, gcc_p) \
+  (!(gcc_p) \
+   && (n_opt_found \
+       || function_stab_type == N_STSYM \
+       || function_stab_type == N_GSYM))
+
+/* Sequence of bytes for breakpoint instruction (ta 1). */
+
+#define BREAKPOINT {0x91, 0xd0, 0x20, 0x01}
+
+/* Register numbers of various important registers.
+   Note that some of these values are "real" register numbers,
+   and correspond to the general registers of the machine,
+   and some are "phony" register numbers which are too large
+   to be actual register numbers as far as the user is concerned
+   but do serve to get the desired values when passed to read_register.  */
+
+#define	G0_REGNUM 0		/* %g0 */
+#define	G1_REGNUM 1		/* %g1 */
+#define O0_REGNUM 8		/* %o0 */
+#define	RP_REGNUM 15		/* Contains return address value, *before* \
+				   any windows get switched.  */
+#define	O7_REGNUM 15		/* Last local reg not saved on stack frame */
+#define	L0_REGNUM 16		/* First local reg that's saved on stack frame
+				   rather than in machine registers */
+#define	I0_REGNUM 24		/* %i0 */
+#define	I7_REGNUM 31		/* Last local reg saved on stack frame */
+#define	PS_REGNUM 65		/* Contains processor status */
+#define PS_FLAG_CARRY 0x100000	/* Carry bit in PS */
+#define	WIM_REGNUM 66		/* Window Invalid Mask (not really supported) */
+#define	TBR_REGNUM 67		/* Trap Base Register (not really supported) */
+#define	FPS_REGNUM 70		/* Floating point status register */
+#define	CPS_REGNUM 71		/* Coprocessor status register */
+
+/* Writing to %g0 is a noop (not an error or exception or anything like
+   that, however).  */
+
+#define CANNOT_STORE_REGISTER(regno) ((regno) == G0_REGNUM)
+
+/*
+ * FRAME_CHAIN and FRAME_INFO definitions, collected here for convenience.
+ */
+
+#if !defined (GDB_MULTI_ARCH) || (GDB_MULTI_ARCH == 0)
+/*
+ * The following defines must go away for MULTI_ARCH.
+ */
 
 /* Describe the pointer in each stack frame to the previous stack frame
    (its caller).  */
@@ -310,64 +451,56 @@ extern CORE_ADDR
 
    GCC 2.6 and later can generate ``flat register window'' code that
    makes frames by explicitly saving those registers that need to be
-   saved.  %i7 is used as the frame pointer, and the frame is laid out so
-   that flat and non-flat calls can be intermixed freely within a
-   program.  Unfortunately for GDB, this means it must detect and record
-   the flatness of frames.
+   saved.  %i7 is used as the frame pointer, and the frame is laid out
+   so that flat and non-flat calls can be intermixed freely within a
+   program.  Unfortunately for GDB, this means it must detect and
+   record the flatness of frames.
 
    Since the prologue in a flat frame also tells us where fp and pc
    have been stashed (the frame is of variable size, so their location
    is not fixed), it's convenient to record them in the frame info.  */
 
-#define EXTRA_FRAME_INFO  \
-  CORE_ADDR bottom;  \
-  int in_prologue; \
-  int flat;  \
+#define EXTRA_FRAME_INFO \
+  CORE_ADDR bottom;      \
+  int in_prologue;       \
+  int flat;              \
   /* Following fields only relevant for flat frames.  */ \
-  CORE_ADDR pc_addr;  \
-  CORE_ADDR fp_addr;  \
+  CORE_ADDR pc_addr;     \
+  CORE_ADDR fp_addr;     \
   /* Add this to ->frame to get the value of the stack pointer at the */ \
   /* time of the register saves.  */ \
   int sp_offset;
 
-#define FRAME_INIT_SAVED_REGS(fp)	/*no-op */
+/* We need to override GET_SAVED_REGISTER so that we can deal with the way
+   outs change into ins in different frames.  HAVE_REGISTER_WINDOWS can't
+   deal with this case and also handle flat frames at the same time.  */
 
-#define INIT_EXTRA_FRAME_INFO(fromleaf, fci) \
-  sparc_init_extra_frame_info (fromleaf, fci)
-extern void sparc_init_extra_frame_info PARAMS ((int, struct frame_info *));
+void sparc_get_saved_register PARAMS ((char *raw_buffer, 
+				       int *optimized, 
+				       CORE_ADDR * addrp, 
+				       struct frame_info * frame, 
+				       int regnum, 
+				       enum lval_type * lvalp));
 
-#define	PRINT_EXTRA_FRAME_INFO(fi) \
-  { \
-    if ((fi) && (fi)->flat) \
-      printf_filtered (" flat, pc saved at 0x%s, fp saved at 0x%s\n", \
-                       paddr_nz ((fi)->pc_addr), paddr_nz ((fi)->fp_addr)); \
-  }
+#define GET_SAVED_REGISTER(RAW_BUFFER, OPTIMIZED, ADDRP, FRAME, REGNUM, LVAL) \
+     sparc_get_saved_register (RAW_BUFFER, OPTIMIZED, ADDRP, \
+			       FRAME, REGNUM, LVAL)
 
-#define FRAME_CHAIN(thisframe) (sparc_frame_chain (thisframe))
-extern CORE_ADDR sparc_frame_chain PARAMS ((struct frame_info *));
+#define FRAME_INIT_SAVED_REGS(FP)	/*no-op */
 
-/* INIT_EXTRA_FRAME_INFO needs the PC to detect flat frames.  */
-
-#define	INIT_FRAME_PC(fromleaf, prev)	/* nothing */
-#define INIT_FRAME_PC_FIRST(fromleaf, prev) \
-  (prev)->pc = ((fromleaf) ? SAVED_PC_AFTER_CALL ((prev)->next) : \
-	      (prev)->next ? FRAME_SAVED_PC ((prev)->next) : read_pc ());
+#define INIT_EXTRA_FRAME_INFO(FROMLEAF, FCI) \
+     sparc_init_extra_frame_info (FROMLEAF, FCI)
+extern void sparc_init_extra_frame_info PARAMS ((int, struct frame_info *));
 
-/* Define other aspects of the stack frame.  */
+#define FRAME_CHAIN(THISFRAME) (sparc_frame_chain (THISFRAME))
+extern CORE_ADDR sparc_frame_chain PARAMS ((struct frame_info *));
 
 /* A macro that tells us whether the function invocation represented
    by FI does not have a frame on the stack associated with it.  If it
    does not, FRAMELESS is set to 1, else 0.  */
-#define FRAMELESS_FUNCTION_INVOCATION(FI) \
-  (frameless_look_for_prologue(FI))
 
-/* The location of I0 w.r.t SP.  This is actually dependent on how the system's
-   window overflow/underflow routines are written.  Most vendors save the L regs
-   followed by the I regs (at the higher address).  Some vendors get it wrong.
- */
-
-#define	FRAME_SAVED_L0	0
-#define	FRAME_SAVED_I0	(8 * REGISTER_RAW_SIZE (L0_REGNUM))
+#define FRAMELESS_FUNCTION_INVOCATION(FI) \
+     frameless_look_for_prologue (FI)
 
 /* Where is the PC for a specific frame */
 
@@ -375,23 +508,46 @@ extern CORE_ADDR sparc_frame_chain PARAMS ((struct frame_info *));
 extern CORE_ADDR sparc_frame_saved_pc PARAMS ((struct frame_info *));
 
 /* If the argument is on the stack, it will be here.  */
-#define FRAME_ARGS_ADDRESS(fi) ((fi)->frame)
+#define FRAME_ARGS_ADDRESS(FI) ((FI)->frame)
 
-#define FRAME_STRUCT_ARGS_ADDRESS(fi) ((fi)->frame)
-
-#define FRAME_LOCALS_ADDRESS(fi) ((fi)->frame)
+#define FRAME_LOCALS_ADDRESS(FI) ((FI)->frame)
 
 /* Set VAL to the number of args passed to frame described by FI.
    Can set VAL to -1, meaning no way to tell.  */
 
 /* We can't tell how many args there are
    now that the C compiler delays popping them.  */
-#define FRAME_NUM_ARGS(fi) (-1)
+#define FRAME_NUM_ARGS(FI) (-1)
 
 /* Return number of bytes at start of arglist that are not really args.  */
 
 #define FRAME_ARGS_SKIP 68
-
+
+#endif /* GDB_MULTI_ARCH */
+
+#define	PRINT_EXTRA_FRAME_INFO(FI) \
+     sparc_print_extra_frame_info (FI)
+extern void sparc_print_extra_frame_info (struct frame_info *);
+
+/* INIT_EXTRA_FRAME_INFO needs the PC to detect flat frames.  */
+
+#define	INIT_FRAME_PC(FROMLEAF, PREV)	/* nothing */
+#define INIT_FRAME_PC_FIRST(FROMLEAF, PREV) \
+  (PREV)->pc = ((FROMLEAF) ? SAVED_PC_AFTER_CALL ((PREV)->next) : \
+	      (PREV)->next ? FRAME_SAVED_PC ((PREV)->next) : read_pc ());
+
+/* Define other aspects of the stack frame.  */
+
+/* The location of I0 w.r.t SP.  This is actually dependent on how the
+   system's window overflow/underflow routines are written.  Most
+   vendors save the L regs followed by the I regs (at the higher
+   address).  Some vendors get it wrong.  */
+
+#define	FRAME_SAVED_L0	0
+#define	FRAME_SAVED_I0	(8 * REGISTER_RAW_SIZE (L0_REGNUM))
+
+#define FRAME_STRUCT_ARGS_ADDRESS(FI) ((FI)->frame)
+
 /* Things needed for making the inferior call functions.  */
 /*
  * First of all, let me give my opinion of what the DUMMY_FRAME
@@ -455,20 +611,13 @@ extern CORE_ADDR sparc_frame_saved_pc PARAMS ((struct frame_info *));
  * CALL_DUMMY, as directed by call_function).
  */
 
-/* Push an empty stack frame, to record the current PC, etc.  */
-
-#define PUSH_DUMMY_FRAME	sparc_push_dummy_frame ()
-#define POP_FRAME	sparc_pop_frame ()
-
-void sparc_push_dummy_frame PARAMS ((void)), sparc_pop_frame PARAMS ((void));
-
 #ifndef CALL_DUMMY
 /* This sequence of words is the instructions
 
-   0:   bc 10 00 01     mov  %g1, %fp
-   4:   9d e3 80 00     save  %sp, %g0, %sp
-   8:   bc 10 00 02     mov  %g2, %fp
-   c:   be 10 00 03     mov  %g3, %i7
+   00:   bc 10 00 01     mov  %g1, %fp
+   04:   9d e3 80 00     save  %sp, %g0, %sp
+   08:   bc 10 00 02     mov  %g2, %fp
+   0c:   be 10 00 03     mov  %g3, %i7
    10:   da 03 a0 58     ld  [ %sp + 0x58 ], %o5
    14:   d8 03 a0 54     ld  [ %sp + 0x54 ], %o4
    18:   d6 03 a0 50     ld  [ %sp + 0x50 ], %o3
@@ -485,7 +634,12 @@ void sparc_push_dummy_frame PARAMS ((void)), sparc_pop_frame PARAMS ((void));
    * this is a multiple of 8 (not only 4) bytes.
    * the `call' insn is a relative, not an absolute call.
    * the `nop' at the end is needed to keep the trap from
-   clobbering things (if NPC pointed to garbage instead).
+     clobbering things (if NPC pointed to garbage instead).
+ */
+
+#if !defined (GDB_MULTI_ARCH) || (GDB_MULTI_ARCH == 0)
+/*
+ * The following defines must go away for MULTI_ARCH.
  */
 
 #define CALL_DUMMY { 0xbc100001, 0x9de38000, 0xbc100002, 0xbe100003,	\
@@ -506,26 +660,86 @@ void sparc_push_dummy_frame PARAMS ((void)), sparc_pop_frame PARAMS ((void));
 
 #define CALL_DUMMY_CALL_OFFSET (CALL_DUMMY_START_OFFSET + 0x24)
 
-/* Offset within CALL_DUMMY of the 'ta 1' instruction. */
+/* Offset within CALL_DUMMY of the 'ta 1' trap instruction. */
 
 #define CALL_DUMMY_BREAKPOINT_OFFSET (CALL_DUMMY_START_OFFSET + 0x30)
 
 #define CALL_DUMMY_STACK_ADJUST 68
 
-#endif
+/* Call dummy method (eg. on stack, at entry point, etc.) */
+
+#define CALL_DUMMY_LOCATION ON_STACK
+
+/* Method for detecting dummy frames.  */
+
+#define PC_IN_CALL_DUMMY(PC, SP, FRAME_ADDRESS) \
+     pc_in_call_dummy_on_stack (PC, SP, FRAME_ADDRESS)
+
+#endif /* GDB_MULTI_ARCH */
+
+#endif /* CALL_DUMMY */
+
+#if !defined (GDB_MULTI_ARCH) || (GDB_MULTI_ARCH == 0)
+/*
+ * The following defines must go away for MULTI_ARCH. 
+ */
+
 /* Insert the specified number of args and function address
    into a call sequence of the above form stored at DUMMYNAME.  */
 
-#define FIX_CALL_DUMMY(dummyname, pc, fun, nargs, args, type, gcc_p) \
- sparc_fix_call_dummy (dummyname, pc, fun, type, gcc_p)
+#define FIX_CALL_DUMMY(DUMMYNAME, PC, FUN, NARGS, ARGS, TYPE, GCC_P) \
+     sparc_fix_call_dummy (DUMMYNAME, PC, FUN, TYPE, GCC_P)
 void sparc_fix_call_dummy PARAMS ((char *dummy, CORE_ADDR pc, CORE_ADDR fun,
 				   struct type * value_type, int using_gcc));
 
-/* The Sparc returns long doubles on the stack.  */
+/* Arguments smaller than an int must be promoted to ints when
+   synthesizing function calls.  */
+
+/* Push an empty stack frame, to record the current PC, etc.  */
+
+#define PUSH_DUMMY_FRAME	sparc_push_dummy_frame ()
+#define POP_FRAME		sparc_pop_frame ()
+
+void sparc_push_dummy_frame PARAMS ((void));
+void sparc_pop_frame PARAMS ((void));
+
+#define PUSH_ARGUMENTS(NARGS, ARGS, SP, STRUCT_RETURN, STRUCT_ADDR) \
+     sparc32_push_arguments (NARGS, ARGS, SP, STRUCT_RETURN, STRUCT_ADDR)
+
+extern CORE_ADDR
+sparc32_push_arguments PARAMS ((int, 
+				struct value **, 
+				CORE_ADDR, 
+				int, 
+				CORE_ADDR));
+
+/* Store the address of the place in which to copy the structure the
+   subroutine will return.  This is called from call_function_by_hand. 
+   The ultimate mystery is, tho, what is the value "16"?  */
+
+#define STORE_STRUCT_RETURN(ADDR, SP) \
+  { char val[4]; \
+    store_unsigned_integer (val, 4, (ADDR)); \
+    write_memory ((SP)+(16*4), val, 4); }
+
+/* Default definition of USE_STRUCT_CONVENTION.  */
+
+#ifndef USE_STRUCT_CONVENTION
+#define USE_STRUCT_CONVENTION(GCC_P, TYPE) \
+     generic_use_struct_convention (GCC_P, TYPE)
+#endif
+
+/* Extract from an array REGBUF containing the (raw) register state a
+   function return value of type TYPE, and copy that, in virtual
+   format, into VALBUF.  */
+
+#define EXTRACT_RETURN_VALUE(TYPE, REGBUF, VALBUF) \
+     sparc32_extract_return_value (TYPE, REGBUF, VALBUF)
+extern void
+sparc32_extract_return_value PARAMS ((struct type *, char[], char *));
+
+#endif /* GDB_MULTI_ARCH */
 
-#define RETURN_VALUE_ON_STACK(TYPE) \
-  (TYPE_CODE(TYPE) == TYPE_CODE_FLT \
-   && TYPE_LENGTH(TYPE) > 8)
 
 /* Sparc has no reliable single step ptrace call */
 
@@ -548,7 +762,6 @@ extern struct frame_info *setup_arbitrary_frame PARAMS ((int, CORE_ADDR *));
   sparc_print_register_hook (regno)
 extern void sparc_print_register_hook PARAMS ((int regno));
 
-
 /* Optimization for storing registers to the inferior.  The hook
    DO_DEFERRED_STORES
    actually executes any deferred stores.  It is called any time
@@ -564,21 +777,7 @@ extern int deferred_stores;
 #define	CLEAR_DEFERRED_STORES	\
   deferred_stores = 0;
 
-/* If the current gcc for for this target does not produce correct debugging
-   information for float parameters, both prototyped and unprototyped, then
-   define this macro.  This forces gdb to  always assume that floats are
-   passed as doubles and then converted in the callee. */
-
-#define COERCE_FLOAT_TO_DOUBLE(formal, actual) (1)
-
 /* Select the sparc disassembler */
 
 #define TM_PRINT_INSN_MACH bfd_mach_sparc
 
-/* Arguments smaller than an int must promoted to ints when synthesizing
-   function calls.  */
-
-#define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \
-  (sparc_push_arguments((nargs), (args), (sp), (struct_return), (struct_addr)))
-extern CORE_ADDR
-  sparc_push_arguments PARAMS ((int, struct value **, CORE_ADDR, int, CORE_ADDR));
diff --git a/gdb/config/sparc/tm-sparclet.h b/gdb/config/sparc/tm-sparclet.h
index 2cec512..3684f74 100644
--- a/gdb/config/sparc/tm-sparclet.h
+++ b/gdb/config/sparc/tm-sparclet.h
@@ -18,9 +18,25 @@
    Foundation, Inc., 59 Temple Place - Suite 330,
    Boston, MA 02111-1307, USA.  */
 
+#define TARGET_SPARCLET 1	/* Still needed for non-multi-arch case */
+
 #include "sparc/tm-sparc.h"
 
-#define TARGET_SPARCLET 1
+/* Note: we are not defining GDB_MULTI_ARCH for the sparclet target
+   at this time, because we have not figured out how to detect the
+   sparclet target from the bfd structure.  */
+
+/* Sparclet regs, for debugging purposes.  */
+
+enum { 
+  CCSR_REGNUM   = 72,
+  CCPR_REGNUM   = 73, 
+  CCCRCR_REGNUM = 74,
+  CCOR_REGNUM   = 75, 
+  CCOBR_REGNUM  = 76,
+  CCIBR_REGNUM  = 77,
+  CCIR_REGNUM   = 78
+};
 
 /* Select the sparclet disassembler.  Slightly different instruction set from
    the V8 sparc.  */
@@ -38,6 +54,11 @@
 #define BIG_BREAKPOINT {0x91, 0xd0, 0x20, 0x01}
 #define LITTLE_BREAKPOINT {0x01, 0x20, 0xd0, 0x91}
 
+#if !defined (GDB_MULTI_ARCH) || (GDB_MULTI_ARCH == 0)
+/*
+ * The following defines must go away for MULTI_ARCH.
+ */
+
 #undef  NUM_REGS		/* formerly "72" */
 /*                WIN  FP   CPU  CCP  ASR  AWR  APSR */
 #define NUM_REGS (32 + 32 + 8  + 8  + 8/*+ 32 + 1*/)
@@ -80,7 +101,7 @@
 
 /* Remove FP dependant code which was defined in tm-sparc.h */
 #undef	FP0_REGNUM		/* Floating point register 0 */
-#undef	FPS_REGNUM		/* Floating point status register */
+#undef  FPS_REGNUM		/* Floating point status register */
 #undef 	CPS_REGNUM		/* Coprocessor status register */
 
 /* sparclet register numbers */
@@ -103,6 +124,8 @@
 			  TYPE_LENGTH (TYPE));                         \
   }
 
+#endif /* GDB_MULTI_ARCH */
+
 #undef PRINT_REGISTER_HOOK
 #define PRINT_REGISTER_HOOK(regno)
 
diff --git a/gdb/config/sparc/tm-sparclite.h b/gdb/config/sparc/tm-sparclite.h
index 2e63418..1ccb370 100644
--- a/gdb/config/sparc/tm-sparclite.h
+++ b/gdb/config/sparc/tm-sparclite.h
@@ -18,10 +18,27 @@
    Foundation, Inc., 59 Temple Place - Suite 330,
    Boston, MA 02111-1307, USA.  */
 
-#define TARGET_SPARCLITE 1
+#define TARGET_SPARCLITE 1	/* Still needed for non-multi-arch case */
 
 #include "sparc/tm-sparc.h"
 
+/* Note: we are not defining GDB_MULTI_ARCH for the sparclet target
+   at this time, because we have not figured out how to detect the
+   sparclet target from the bfd structure.  */
+
+/* Sparclite regs, for debugging purposes */
+
+enum {
+  DIA1_REGNUM = 72,		/* debug instr address register 1 */
+  DIA2_REGNUM = 73,		/* debug instr address register 2 */
+  DDA1_REGNUM = 74,		/* debug data address register 1 */
+  DDA2_REGNUM = 75,		/* debug data address register 2 */
+  DDV1_REGNUM = 76,		/* debug data value register 1 */
+  DDV2_REGNUM = 77,		/* debug data value register 2 */
+  DCR_REGNUM  = 78,		/* debug control register */
+  DSR_REGNUM  = 79		/* debug status regsiter */
+};
+
 /* overrides of tm-sparc.h */
 
 #undef TARGET_BYTE_ORDER
@@ -39,7 +56,13 @@
 
 #define DECR_PC_AFTER_HW_BREAK 4
 
-#define FRAME_CHAIN_VALID(fp,fi) func_frame_chain_valid (fp, fi)
+#if !defined (GDB_MULTI_ARCH) || (GDB_MULTI_ARCH == 0)
+/*
+ * The following defines must go away for MULTI_ARCH.
+ */
+
+#undef  FRAME_CHAIN_VALID
+#define FRAME_CHAIN_VALID(FP,FI) func_frame_chain_valid (FP, FI)
 
 #undef NUM_REGS
 #define NUM_REGS 80
@@ -71,6 +94,8 @@
 #define DCR_REGNUM 78		/* debug control register */
 #define DSR_REGNUM 79		/* debug status regsiter */
 
+#endif /* GDB_MULTI_ARCH */
+
 #define TARGET_HW_BREAK_LIMIT 2
 #define TARGET_HW_WATCH_LIMIT 2
 
diff --git a/gdb/config/sparc/tm-sun4sol2.h b/gdb/config/sparc/tm-sun4sol2.h
index a432d61..dc487d4 100644
--- a/gdb/config/sparc/tm-sun4sol2.h
+++ b/gdb/config/sparc/tm-sun4sol2.h
@@ -19,6 +19,8 @@
    Foundation, Inc., 59 Temple Place - Suite 330,
    Boston, MA 02111-1307, USA.  */
 
+/*#define GDB_MULTI_ARCH 2*/
+
 #include "sparc/tm-sparc.h"
 #include "tm-sysv4.h"
 
diff --git a/gdb/sparc-tdep.c b/gdb/sparc-tdep.c
index ceac802..dd09d1e 100644
--- a/gdb/sparc-tdep.c
+++ b/gdb/sparc-tdep.c
@@ -22,6 +22,7 @@
 /* ??? Support for calling functions from gdb in sparc64 is unfinished.  */
 
 #include "defs.h"
+#include "arch-utils.h"
 #include "frame.h"
 #include "inferior.h"
 #include "obstack.h"
@@ -36,15 +37,39 @@
 
 #include "gdbcore.h"
 
+#include "symfile.h" 	/* for 'entry_point_address' */
+
+/*
+ * Some local macros that have multi-arch and non-multi-arch versions:
+ */
+
+#if (GDB_MULTI_ARCH > 0)
+
+/* Does the target have Floating Point registers?  */
+#define SPARC_HAS_FPU     (gdbarch_tdep (current_gdbarch)->has_fpu)
+/* Number of bytes devoted to Floating Point registers: */
+#define FP_REGISTER_BYTES (gdbarch_tdep (current_gdbarch)->fp_register_bytes)
+/* Highest numbered Floating Point register.  */
+#define FP_MAX_REGNUM     (gdbarch_tdep (current_gdbarch)->fp_max_regnum)
+/* Size of a general (integer) register: */
+#define SPARC_INTREG_SIZE (gdbarch_tdep (current_gdbarch)->intreg_size)
+/* Offset within the call dummy stack of the saved registers.  */
+#define DUMMY_REG_SAVE_OFFSET (gdbarch_tdep (current_gdbarch)->reg_save_offset)
+
+#else /* non-multi-arch */
+
+
+/* Does the target have Floating Point registers?  */
 #if defined(TARGET_SPARCLET) || defined(TARGET_SPARCLITE)
 #define SPARC_HAS_FPU 0
 #else
 #define SPARC_HAS_FPU 1
 #endif
 
-#ifdef GDB_TARGET_IS_SPARC64
+/* Number of bytes devoted to Floating Point registers: */
+#if (GDB_TARGET_IS_SPARC64)
 #define FP_REGISTER_BYTES (64 * 4)
-#else 
+#else
 #if (SPARC_HAS_FPU)
 #define FP_REGISTER_BYTES (32 * 4)
 #else
@@ -52,13 +77,45 @@
 #endif
 #endif
 
-/* If not defined, assume 32 bit sparc.  */
-#ifndef FP_MAX_REGNUM
+/* Highest numbered Floating Point register.  */
+#if (GDB_TARGET_IS_SPARC64)
+#define FP_MAX_REGNUM (FP0_REGNUM + 48)
+#else
 #define FP_MAX_REGNUM (FP0_REGNUM + 32)
 #endif
 
+/* Size of a general (integer) register: */
 #define SPARC_INTREG_SIZE (REGISTER_RAW_SIZE (G0_REGNUM))
 
+/* Offset within the call dummy stack of the saved registers.  */
+#if (GDB_TARGET_IS_SPARC64)
+#define DUMMY_REG_SAVE_OFFSET (128 + 16)
+#else
+#define DUMMY_REG_SAVE_OFFSET 0x60
+#endif
+
+#endif /* GDB_MULTI_ARCH */
+
+struct gdbarch_tdep
+  {
+    int has_fpu;
+    int fp_register_bytes;
+    int y_regnum;
+    int fp_max_regnum;
+    int intreg_size;
+    int reg_save_offset;
+    int call_dummy_call_offset;
+    int print_insn_mach;
+  };
+
+/* Now make GDB_TARGET_IS_SPARC64 a runtime test.  */
+/* FIXME MVS: or try testing bfd_arch_info.arch and bfd_arch_info.mach ... 
+ * define GDB_TARGET_IS_SPARC64 \
+ *      (TARGET_ARCHITECTURE->arch == bfd_arch_sparc &&    \
+ *      (TARGET_ARCHITECTURE->mach == bfd_mach_sparc_v9 || \
+ *       TARGET_ARCHITECTURE->mach == bfd_mach_sparc_v9a))
+ */
+
 /* From infrun.c */
 extern int stop_after_trap;
 
@@ -68,7 +125,7 @@ extern int stop_after_trap;
    track of which sets of registers we have locally-changed copies of,
    so we only need send the groups that have changed.  */
 
-int deferred_stores = 0;	/* Cumulates stores we want to do eventually. */
+int deferred_stores = 0;    /* Accumulated stores we want to do eventually. */
 
 
 /* Some machines, such as Fujitsu SPARClite 86x, have a bi-endian mode
@@ -126,12 +183,8 @@ fetch_instruction (pc)
 
 typedef enum
 {
-  Error, not_branch, bicc, bicca, ba, baa, ticc, ta,
-#ifdef GDB_TARGET_IS_SPARC64
-  done_retry
-#endif
-}
-branch_type;
+  Error, not_branch, bicc, bicca, ba, baa, ticc, ta, done_retry
+} branch_type;
 
 /* Simulate single-step ptrace call for sun4.  Code written by Gary
    Beihl (beihl@mcc.com).  */
@@ -143,7 +196,7 @@ static int brknpc4, brktrg;
 typedef char binsn_quantum[BREAKPOINT_MAX];
 static binsn_quantum break_mem[3];
 
-static branch_type isbranch PARAMS ((long, CORE_ADDR, CORE_ADDR *));
+static branch_type isbranch (long, CORE_ADDR, CORE_ADDR *);
 
 /* single_step() is called just before we want to resume the inferior,
    if we want to single-step it but there is no hardware or kernel single-step
@@ -191,13 +244,11 @@ sparc_software_single_step (ignore, insert_breakpoints_p)
 	  brktrg = 1;
 	  target_insert_breakpoint (target, break_mem[2]);
 	}
-#ifdef GDB_TARGET_IS_SPARC64
-      else if (br == done_retry)
+      else if (GDB_TARGET_IS_SPARC64 && br == done_retry)
 	{
 	  brktrg = 1;
 	  target_insert_breakpoint (target, break_mem[2]);
 	}
-#endif
     }
   else
     {
@@ -212,11 +263,24 @@ sparc_software_single_step (ignore, insert_breakpoints_p)
     }
 }
 
-/* Call this for each newly created frame.  For SPARC, we need to calculate
-   the bottom of the frame, and do some extra work if the prologue
-   has been generated via the -mflat option to GCC.  In particular,
-   we need to know where the previous fp and the pc have been stashed,
-   since their exact position within the frame may vary.  */
+struct frame_extra_info 
+{
+  CORE_ADDR bottom;
+  int in_prologue;
+  int flat;
+  /* Following fields only relevant for flat frames.  */
+  CORE_ADDR pc_addr;
+  CORE_ADDR fp_addr;
+  /* Add this to ->frame to get the value of the stack pointer at the 
+     time of the register saves.  */
+  int sp_offset;
+};
+
+/* Call this for each newly created frame.  For SPARC, we need to
+   calculate the bottom of the frame, and do some extra work if the
+   prologue has been generated via the -mflat option to GCC.  In
+   particular, we need to know where the previous fp and the pc have
+   been stashed, since their exact position within the frame may vary.  */
 
 void
 sparc_init_extra_frame_info (fromleaf, fi)
@@ -227,16 +291,22 @@ sparc_init_extra_frame_info (fromleaf, fi)
   CORE_ADDR prologue_start, prologue_end;
   int insn;
 
-  fi->bottom =
+  fi->extra_info = (struct frame_extra_info *)
+    frame_obstack_alloc (sizeof (struct frame_extra_info));
+  frame_saved_regs_zalloc (fi);
+
+  fi->extra_info->bottom =
     (fi->next ?
-     (fi->frame == fi->next->frame ? fi->next->bottom : fi->next->frame) :
-     read_sp ());
+     (fi->frame == fi->next->frame ? fi->next->extra_info->bottom : 
+      fi->next->frame) : read_sp ());
 
   /* If fi->next is NULL, then we already set ->frame by passing read_fp()
      to create_new_frame.  */
   if (fi->next)
     {
-      char buf[MAX_REGISTER_RAW_SIZE];
+      char *buf;
+
+      buf = alloca (MAX_REGISTER_RAW_SIZE);
 
       /* Compute ->frame as if not flat.  If it is flat, we'll change
          it later.  */
@@ -248,25 +318,23 @@ sparc_init_extra_frame_info (fromleaf, fi)
 	  /* A frameless function interrupted by a signal did not change
 	     the frame pointer, fix up frame pointer accordingly.  */
 	  fi->frame = FRAME_FP (fi->next);
-	  fi->bottom = fi->next->bottom;
+	  fi->extra_info->bottom = fi->next->extra_info->bottom;
 	}
       else
 	{
 	  /* Should we adjust for stack bias here? */
 	  get_saved_register (buf, 0, 0, fi, FP_REGNUM, 0);
 	  fi->frame = extract_address (buf, REGISTER_RAW_SIZE (FP_REGNUM));
-#ifdef GDB_TARGET_IS_SPARC64
-	  if (fi->frame & 1)
-	    fi->frame += 2047;
-#endif
 
+	  if (GDB_TARGET_IS_SPARC64 && (fi->frame & 1))
+	    fi->frame += 2047;
 	}
     }
 
   /* Decide whether this is a function with a ``flat register window''
      frame.  For such functions, the frame pointer is actually in %i7.  */
-  fi->flat = 0;
-  fi->in_prologue = 0;
+  fi->extra_info->flat = 0;
+  fi->extra_info->in_prologue = 0;
   if (find_pc_partial_function (fi->pc, &name, &prologue_start, &prologue_end))
     {
       /* See if the function starts with an add (which will be of a
@@ -286,31 +354,35 @@ sparc_init_extra_frame_info (fromleaf, fi)
 	      && X_OP3 (insn) == 4
 	      && X_RS1 (insn) == 14)
 	    {
-	      char buf[MAX_REGISTER_RAW_SIZE];
+	      char *buf;
+	      
+	      buf = alloca (MAX_REGISTER_RAW_SIZE);
 
 	      /* We definitely have a flat frame now.  */
-	      fi->flat = 1;
+	      fi->extra_info->flat = 1;
 
-	      fi->sp_offset = offset;
+	      fi->extra_info->sp_offset = offset;
 
 	      /* Overwrite the frame's address with the value in %i7.  */
 	      get_saved_register (buf, 0, 0, fi, I7_REGNUM, 0);
 	      fi->frame = extract_address (buf, REGISTER_RAW_SIZE (I7_REGNUM));
-#ifdef GDB_TARGET_IS_SPARC64
-	      if (fi->frame & 1)
+
+	      if (GDB_TARGET_IS_SPARC64 && (fi->frame & 1))
 		fi->frame += 2047;
-#endif
+
 	      /* Record where the fp got saved.  */
-	      fi->fp_addr = fi->frame + fi->sp_offset + X_SIMM13 (insn);
+	      fi->extra_info->fp_addr = 
+		fi->frame + fi->extra_info->sp_offset + X_SIMM13 (insn);
 
 	      /* Also try to collect where the pc got saved to.  */
-	      fi->pc_addr = 0;
+	      fi->extra_info->pc_addr = 0;
 	      insn = fetch_instruction (prologue_start + 12);
 	      if (X_OP (insn) == 3
 		  && X_RD (insn) == 15
 		  && X_OP3 (insn) == 4
 		  && X_RS1 (insn) == 14)
-		fi->pc_addr = fi->frame + fi->sp_offset + X_SIMM13 (insn);
+		fi->extra_info->pc_addr = 
+		  fi->frame + fi->extra_info->sp_offset + X_SIMM13 (insn);
 	    }
 	}
       else
@@ -337,7 +409,7 @@ sparc_init_extra_frame_info (fromleaf, fi)
 		}
 	      if (addr >= fi->pc)
 		{
-		  fi->in_prologue = 1;
+		  fi->extra_info->in_prologue = 1;
 		  fi->frame = read_register (SP_REGNUM);
 		}
 	    }
@@ -363,7 +435,7 @@ sparc_frame_chain (frame)
 
 CORE_ADDR
 sparc_extract_struct_value_address (regbuf)
-     char regbuf[REGISTER_BYTES];
+     char *regbuf;
 {
   return extract_address (regbuf + REGISTER_BYTE (O0_REGNUM),
 			  REGISTER_RAW_SIZE (O0_REGNUM));
@@ -375,9 +447,10 @@ CORE_ADDR
 sparc_frame_saved_pc (frame)
      struct frame_info *frame;
 {
-  char buf[MAX_REGISTER_RAW_SIZE];
+  char *buf;
   CORE_ADDR addr;
 
+  buf = alloca (MAX_REGISTER_RAW_SIZE);
   if (frame->signal_handler_caller)
     {
       /* This is the signal trampoline frame.
@@ -388,10 +461,12 @@ sparc_frame_saved_pc (frame)
 #endif
 
       CORE_ADDR sigcontext_addr;
-      char scbuf[TARGET_PTR_BIT / HOST_CHAR_BIT];
+      char *scbuf;
       int saved_pc_offset = SIGCONTEXT_PC_OFFSET;
       char *name = NULL;
 
+      scbuf = alloca (TARGET_PTR_BIT / HOST_CHAR_BIT);
+
       /* Solaris2 ucbsigvechandler passes a pointer to a sigcontext
          as the third parameter.  The offset to the saved pc is 12.  */
       find_pc_partial_function (frame->pc, &name,
@@ -410,11 +485,11 @@ sparc_frame_saved_pc (frame)
 			  scbuf, sizeof (scbuf));
       return extract_address (scbuf, sizeof (scbuf));
     }
-  else if (frame->in_prologue ||
-	   (frame->next != NULL
-	    && (frame->next->signal_handler_caller
-		|| frame_in_dummy (frame->next))
-	    && frameless_look_for_prologue (frame)))
+  else if (frame->extra_info->in_prologue ||
+	   (frame->next != NULL &&
+	    (frame->next->signal_handler_caller ||
+	     frame_in_dummy (frame->next)) &&
+	    frameless_look_for_prologue (frame)))
     {
       /* A frameless function interrupted by a signal did not save
          the PC, it is still in %o7.  */
@@ -422,10 +497,10 @@ sparc_frame_saved_pc (frame)
 			  frame, O7_REGNUM, (enum lval_type *) NULL);
       return PC_ADJUST (extract_address (buf, SPARC_INTREG_SIZE));
     }
-  if (frame->flat)
-    addr = frame->pc_addr;
+  if (frame->extra_info->flat)
+    addr = frame->extra_info->pc_addr;
   else
-    addr = frame->bottom + FRAME_SAVED_I0 +
+    addr = frame->extra_info->bottom + FRAME_SAVED_I0 +
       SPARC_INTREG_SIZE * (I7_REGNUM - I0_REGNUM);
 
   if (addr == 0)
@@ -460,7 +535,7 @@ setup_arbitrary_frame (argc, argv)
   if (!frame)
     internal_error ("create_new_frame returned invalid frame");
 
-  frame->bottom = argv[1];
+  frame->extra_info->bottom = argv[1];
   frame->pc = FRAME_SAVED_PC (frame);
   return frame;
 }
@@ -474,15 +549,15 @@ setup_arbitrary_frame (argc, argv)
    This routine should be more specific in its actions; making sure
    that it uses the same register in the initial prologue section.  */
 
-static CORE_ADDR examine_prologue PARAMS ((CORE_ADDR, int, struct frame_info *,
-					   struct frame_saved_regs *));
+static CORE_ADDR examine_prologue (CORE_ADDR, int, struct frame_info *,
+				   CORE_ADDR *);
 
 static CORE_ADDR
 examine_prologue (start_pc, frameless_p, fi, saved_regs)
      CORE_ADDR start_pc;
      int frameless_p;
      struct frame_info *fi;
-     struct frame_saved_regs *saved_regs;
+     CORE_ADDR *saved_regs;
 {
   int insn;
   int dest = -1;
@@ -560,26 +635,52 @@ examine_prologue (start_pc, frameless_p, fi, saved_regs)
   while (1)
     {
       /* Recognize stores into the frame from the input registers.
-         This recognizes all non alternate stores of input register,
-         into a location offset from the frame pointer.  */
-      if ((X_OP (insn) == 3
-	   && (X_OP3 (insn) & 0x3c) == 4	/* Store, non-alternate.  */
-	   && (X_RD (insn) & 0x18) == 0x18	/* Input register.  */
-	   && X_I (insn)	/* Immediate mode.  */
-	   && X_RS1 (insn) == 30	/* Off of frame pointer.  */
-      /* Into reserved stack space.  */
-	   && X_SIMM13 (insn) >= 0x44
-	   && X_SIMM13 (insn) < 0x5b))
-	;
+         This recognizes all non alternate stores of an input register,
+         into a location offset from the frame pointer between
+	 +68 and +92.  */
+
+      /* The above will fail for arguments that are promoted 
+	 (eg. shorts to ints or floats to doubles), because the compiler
+	 will pass them in positive-offset frame space, but the prologue
+	 will save them (after conversion) in negative frame space at an
+	 unpredictable offset.  Therefore I am going to remove the 
+	 restriction on the target-address of the save, on the theory
+	 that any unbroken sequence of saves from input registers must
+	 be part of the prologue.  In un-optimized code (at least), I'm
+	 fairly sure that the compiler would emit SOME other instruction
+	 (eg. a move or add) before emitting another save that is actually
+	 a part of the function body.
+
+	 Besides, the reserved stack space is different for SPARC64 anyway.
+
+	 MVS  4/23/2000  */
+
+      if (X_OP (insn) == 3
+	  && (X_OP3 (insn) & 0x3c)	 == 4	/* Store, non-alternate.  */
+	  && (X_RD (insn) & 0x18) == 0x18	/* Input register.  */
+	  && X_I (insn)				/* Immediate mode.  */
+	  && X_RS1 (insn) == 30)		/* Off of frame pointer.  */
+	; /* empty statement -- fall thru to end of loop */
+      else if (GDB_TARGET_IS_SPARC64
+	       && X_OP (insn) == 3
+	       && (X_OP3 (insn) & 0x3c) == 12	/* store, extended (64-bit) */
+	       && (X_RD (insn) & 0x18) == 0x18	/* input register */
+	       && X_I (insn)			/* immediate mode */
+	       && X_RS1 (insn) == 30)		/* off of frame pointer */
+	; /* empty statement -- fall thru to end of loop */
+      else if (X_OP (insn) == 3
+	       && (X_OP3 (insn) & 0x3c) == 36	/* store, floating-point */
+	       && X_I (insn)			/* immediate mode */
+	       && X_RS1 (insn) == 30)		/* off of frame pointer */
+	; /* empty statement -- fall thru to end of loop */
       else if (is_flat
 	       && X_OP (insn) == 3
-	       && X_OP3 (insn) == 4
-	       && X_RS1 (insn) == 14
-	)
+	       && X_OP3 (insn) == 4		/* store? */
+	       && X_RS1 (insn) == 14)		/* off of frame pointer */
 	{
 	  if (saved_regs && X_I (insn))
-	    saved_regs->regs[X_RD (insn)] =
-	      fi->frame + fi->sp_offset + X_SIMM13 (insn);
+	    saved_regs[X_RD (insn)] =
+	      fi->frame + fi->extra_info->sp_offset + X_SIMM13 (insn);
 	}
       else
 	break;
@@ -620,10 +721,7 @@ isbranch (instruction, addr, target)
 	  || X_OP2 (instruction) == 1
 	  || X_OP2 (instruction) == 3
 	  || X_OP2 (instruction) == 5
-#ifndef GDB_TARGET_IS_SPARC64
-	  || X_OP2 (instruction) == 7
-#endif
-      ))
+	  || (GDB_TARGET_IS_SPARC64 && X_OP2 (instruction) == 7)))
     {
       if (X_COND (instruction) == 8)
 	val = X_A (instruction) ? baa : ba;
@@ -631,11 +729,12 @@ isbranch (instruction, addr, target)
 	val = X_A (instruction) ? bicca : bicc;
       switch (X_OP2 (instruction))
 	{
+	case 7:
+	if (!GDB_TARGET_IS_SPARC64)
+	  break;
+	/* else fall thru */
 	case 2:
 	case 6:
-#ifndef GDB_TARGET_IS_SPARC64
-	case 7:
-#endif
 	  offset = 4 * X_DISP22 (instruction);
 	  break;
 	case 1:
@@ -648,8 +747,8 @@ isbranch (instruction, addr, target)
 	}
       *target = addr + offset;
     }
-#ifdef GDB_TARGET_IS_SPARC64
-  else if (X_OP (instruction) == 2
+  else if (GDB_TARGET_IS_SPARC64
+	   && X_OP (instruction) == 2
 	   && X_OP3 (instruction) == 62)
     {
       if (X_FCN (instruction) == 0)
@@ -665,7 +764,6 @@ isbranch (instruction, addr, target)
 	  val = done_retry;
 	}
     }
-#endif
 
   return val;
 }
@@ -732,8 +830,10 @@ sparc_get_saved_register (raw_buffer, optimized, addrp, frame, regnum, lval)
 
   while (frame1 != NULL)
     {
-      if (frame1->pc >= (frame1->bottom ? frame1->bottom :
-			 read_sp ())
+      /* FIXME MVS: wrong test for dummy frame at entry.  */
+
+      if (frame1->pc >= (frame1->extra_info->bottom ? 
+			 frame1->extra_info->bottom : read_sp ())
 	  && frame1->pc <= FRAME_FP (frame1))
 	{
 	  /* Dummy frame.  All but the window regs are in there somewhere.
@@ -743,57 +843,57 @@ sparc_get_saved_register (raw_buffer, optimized, addrp, frame, regnum, lval)
 	    addr = frame1->frame + (regnum - G0_REGNUM) * SPARC_INTREG_SIZE
 	      - (FP_REGISTER_BYTES + 8 * SPARC_INTREG_SIZE);
 	  else if (regnum >= I0_REGNUM && regnum < I0_REGNUM + 8)
-	    addr = (frame1->prev->bottom
+	    addr = (frame1->prev->extra_info->bottom
 		    + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE
 		    + FRAME_SAVED_I0);
 	  else if (regnum >= L0_REGNUM && regnum < L0_REGNUM + 8)
-	    addr = (frame1->prev->bottom
+	    addr = (frame1->prev->extra_info->bottom
 		    + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE
 		    + FRAME_SAVED_L0);
 	  else if (regnum >= O0_REGNUM && regnum < O0_REGNUM + 8)
 	    addr = frame1->frame + (regnum - O0_REGNUM) * SPARC_INTREG_SIZE
 	      - (FP_REGISTER_BYTES + 16 * SPARC_INTREG_SIZE);
-	  else if (FP0_REGNUM >= 0 &&
+	  else if (SPARC_HAS_FPU &&
 		   regnum >= FP0_REGNUM && regnum < FP0_REGNUM + 32)
 	    addr = frame1->frame + (regnum - FP0_REGNUM) * 4
 	      - (FP_REGISTER_BYTES);
-#ifdef GDB_TARGET_IS_SPARC64
-	  else if (FP0_REGNUM >= 0 &&
+	  else if (GDB_TARGET_IS_SPARC64 && SPARC_HAS_FPU && 
 		   regnum >= FP0_REGNUM + 32 && regnum < FP_MAX_REGNUM)
 	    addr = frame1->frame + 32 * 4 + (regnum - FP0_REGNUM - 32) * 8
 	      - (FP_REGISTER_BYTES);
-#endif
 	  else if (regnum >= Y_REGNUM && regnum < NUM_REGS)
 	    addr = frame1->frame + (regnum - Y_REGNUM) * SPARC_INTREG_SIZE
 	      - (FP_REGISTER_BYTES + 24 * SPARC_INTREG_SIZE);
 	}
-      else if (frame1->flat)
+      else if (frame1->extra_info->flat)
 	{
 
 	  if (regnum == RP_REGNUM)
-	    addr = frame1->pc_addr;
+	    addr = frame1->extra_info->pc_addr;
 	  else if (regnum == I7_REGNUM)
-	    addr = frame1->fp_addr;
+	    addr = frame1->extra_info->fp_addr;
 	  else
 	    {
 	      CORE_ADDR func_start;
-	      struct frame_saved_regs regs;
-	      memset (&regs, 0, sizeof (regs));
+	      CORE_ADDR *regs;
+
+	      regs = alloca (NUM_REGS * sizeof (CORE_ADDR)); 
+	      memset (regs, 0, NUM_REGS * sizeof (CORE_ADDR));
 
 	      find_pc_partial_function (frame1->pc, NULL, &func_start, NULL);
-	      examine_prologue (func_start, 0, frame1, &regs);
-	      addr = regs.regs[regnum];
+	      examine_prologue (func_start, 0, frame1, regs);
+	      addr = regs[regnum];
 	    }
 	}
       else
 	{
 	  /* Normal frame.  Local and In registers are saved on stack.  */
 	  if (regnum >= I0_REGNUM && regnum < I0_REGNUM + 8)
-	    addr = (frame1->prev->bottom
+	    addr = (frame1->prev->extra_info->bottom
 		    + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE
 		    + FRAME_SAVED_I0);
 	  else if (regnum >= L0_REGNUM && regnum < L0_REGNUM + 8)
-	    addr = (frame1->prev->bottom
+	    addr = (frame1->prev->extra_info->bottom
 		    + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE
 		    + FRAME_SAVED_L0);
 	  else if (regnum >= O0_REGNUM && regnum < O0_REGNUM + 8)
@@ -846,37 +946,39 @@ sparc_get_saved_register (raw_buffer, optimized, addrp, frame, regnum, lval)
 
 /* Definitely see tm-sparc.h for more doc of the frame format here.  */
 
-#ifdef GDB_TARGET_IS_SPARC64
-#define DUMMY_REG_SAVE_OFFSET (128 + 16)
-#else
-#define DUMMY_REG_SAVE_OFFSET 0x60
-#endif
-
 /* See tm-sparc.h for how this is calculated.  */
+
 #define DUMMY_STACK_REG_BUF_SIZE \
      (((8+8+8) * SPARC_INTREG_SIZE) + FP_REGISTER_BYTES)
-#define DUMMY_STACK_SIZE (DUMMY_STACK_REG_BUF_SIZE + DUMMY_REG_SAVE_OFFSET)
+#define DUMMY_STACK_SIZE \
+     (DUMMY_STACK_REG_BUF_SIZE + DUMMY_REG_SAVE_OFFSET)
 
 void
 sparc_push_dummy_frame ()
 {
   CORE_ADDR sp, old_sp;
-  char register_temp[DUMMY_STACK_SIZE];
+  char *register_temp;
+
+  register_temp = alloca (DUMMY_STACK_SIZE);
 
   old_sp = sp = read_sp ();
 
-#ifdef GDB_TARGET_IS_SPARC64
-  /* PC, NPC, CCR, FSR, FPRS, Y, ASI */
-  read_register_bytes (REGISTER_BYTE (PC_REGNUM), &register_temp[0],
-		       REGISTER_RAW_SIZE (PC_REGNUM) * 7);
-  read_register_bytes (REGISTER_BYTE (PSTATE_REGNUM), &register_temp[8],
-		       REGISTER_RAW_SIZE (PSTATE_REGNUM));
-  /* FIXME: not sure what needs to be saved here.  */
-#else
-  /* Y, PS, WIM, TBR, PC, NPC, FPS, CPS regs */
-  read_register_bytes (REGISTER_BYTE (Y_REGNUM), &register_temp[0],
-		       REGISTER_RAW_SIZE (Y_REGNUM) * 8);
-#endif
+  if (GDB_TARGET_IS_SPARC64)
+    {
+      /* PC, NPC, CCR, FSR, FPRS, Y, ASI */
+      read_register_bytes (REGISTER_BYTE (PC_REGNUM), &register_temp[0],
+			   REGISTER_RAW_SIZE (PC_REGNUM) * 7);
+      read_register_bytes (REGISTER_BYTE (PSTATE_REGNUM), 
+			   &register_temp[7 * SPARC_INTREG_SIZE],
+			   REGISTER_RAW_SIZE (PSTATE_REGNUM));
+      /* FIXME: not sure what needs to be saved here.  */
+    }
+  else
+    {
+      /* Y, PS, WIM, TBR, PC, NPC, FPS, CPS regs */
+      read_register_bytes (REGISTER_BYTE (Y_REGNUM), &register_temp[0],
+			   REGISTER_RAW_SIZE (Y_REGNUM) * 8);
+    }
 
   read_register_bytes (REGISTER_BYTE (O0_REGNUM),
 		       &register_temp[8 * SPARC_INTREG_SIZE],
@@ -886,7 +988,7 @@ sparc_push_dummy_frame ()
 		       &register_temp[16 * SPARC_INTREG_SIZE],
 		       SPARC_INTREG_SIZE * 8);
 
-  if (FP0_REGNUM >= 0)
+  if (SPARC_HAS_FPU)
     read_register_bytes (REGISTER_BYTE (FP0_REGNUM),
 			 &register_temp[24 * SPARC_INTREG_SIZE],
 			 FP_REGISTER_BYTES);
@@ -936,7 +1038,7 @@ sparc_push_dummy_frame ()
    ugly duplication between sparc_frame_find_saved_regs and
    get_saved_register.
 
-   Stores, into a struct frame_saved_regs,
+   Stores, into an array of CORE_ADDR, 
    the addresses of the saved registers of frame described by FRAME_INFO.
    This includes special registers such as pc and fp saved in special
    ways in the stack frame.  sp is even more special:
@@ -960,13 +1062,12 @@ sparc_push_dummy_frame ()
    See tm-sparc.h (PUSH_DUMMY_FRAME and friends) for CRITICAL information
    about how this works.  */
 
-static void sparc_frame_find_saved_regs PARAMS ((struct frame_info *,
-						 struct frame_saved_regs *));
+static void sparc_frame_find_saved_regs (struct frame_info *, CORE_ADDR *);
 
 static void
 sparc_frame_find_saved_regs (fi, saved_regs_addr)
      struct frame_info *fi;
-     struct frame_saved_regs *saved_regs_addr;
+     CORE_ADDR *saved_regs_addr;
 {
   register int regnum;
   CORE_ADDR frame_addr = FRAME_FP (fi);
@@ -974,92 +1075,86 @@ sparc_frame_find_saved_regs (fi, saved_regs_addr)
   if (!fi)
     internal_error ("Bad frame info struct in FRAME_FIND_SAVED_REGS");
 
-  memset (saved_regs_addr, 0, sizeof (*saved_regs_addr));
+  memset (saved_regs_addr, 0, NUM_REGS * sizeof (CORE_ADDR));
 
-  if (fi->pc >= (fi->bottom ? fi->bottom :
-		 read_sp ())
+  if (fi->pc >= (fi->extra_info->bottom ? 
+		 fi->extra_info->bottom : read_sp ())
       && fi->pc <= FRAME_FP (fi))
     {
       /* Dummy frame.  All but the window regs are in there somewhere. */
       for (regnum = G1_REGNUM; regnum < G1_REGNUM + 7; regnum++)
-	saved_regs_addr->regs[regnum] =
+	saved_regs_addr[regnum] =
 	  frame_addr + (regnum - G0_REGNUM) * SPARC_INTREG_SIZE
 	  - DUMMY_STACK_REG_BUF_SIZE + 16 * SPARC_INTREG_SIZE;
+
       for (regnum = I0_REGNUM; regnum < I0_REGNUM + 8; regnum++)
-	saved_regs_addr->regs[regnum] =
+	saved_regs_addr[regnum] =
 	  frame_addr + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE
 	  - DUMMY_STACK_REG_BUF_SIZE + 8 * SPARC_INTREG_SIZE;
-      if (FP0_REGNUM >= 0)
-	{
-	  for (regnum = FP0_REGNUM; regnum < FP0_REGNUM + 32; regnum++)
-	    saved_regs_addr->regs[regnum] =
-	      frame_addr + (regnum - FP0_REGNUM) * 4
-	      - DUMMY_STACK_REG_BUF_SIZE + 24 * SPARC_INTREG_SIZE;
-#ifdef GDB_TARGET_IS_SPARC64
-	  for (regnum = FP0_REGNUM + 32; regnum < FP_MAX_REGNUM; regnum++)
-	    saved_regs_addr->regs[regnum] =
-	      frame_addr + 32 * 4 + (regnum - FP0_REGNUM - 32) * 4
-	      - DUMMY_STACK_REG_BUF_SIZE + 24 * SPARC_INTREG_SIZE;
-#endif
-	}
 
-#ifdef GDB_TARGET_IS_SPARC64
-      for (regnum = PC_REGNUM; regnum < PC_REGNUM + 7; regnum++)
+      if (SPARC_HAS_FPU)
+	for (regnum = FP0_REGNUM; regnum < FP_MAX_REGNUM; regnum++)
+	  saved_regs_addr[regnum] = frame_addr + (regnum - FP0_REGNUM) * 4
+	    - DUMMY_STACK_REG_BUF_SIZE + 24 * SPARC_INTREG_SIZE;
+
+      if (GDB_TARGET_IS_SPARC64)
 	{
-	  saved_regs_addr->regs[regnum] =
-	    frame_addr + (regnum - PC_REGNUM) * SPARC_INTREG_SIZE
-	    - DUMMY_STACK_REG_BUF_SIZE;
+	  for (regnum = PC_REGNUM; regnum < PC_REGNUM + 7; regnum++)
+	    {
+	      saved_regs_addr[regnum] =
+		frame_addr + (regnum - PC_REGNUM) * SPARC_INTREG_SIZE
+		- DUMMY_STACK_REG_BUF_SIZE;
+	    }
+	  saved_regs_addr[PSTATE_REGNUM] =
+	    frame_addr + 8 * SPARC_INTREG_SIZE - DUMMY_STACK_REG_BUF_SIZE;
 	}
-      saved_regs_addr->regs[PSTATE_REGNUM] =
-	frame_addr + 8 * SPARC_INTREG_SIZE - DUMMY_STACK_REG_BUF_SIZE;
-#else
-      for (regnum = Y_REGNUM; regnum < NUM_REGS; regnum++)
-	saved_regs_addr->regs[regnum] =
-	  frame_addr + (regnum - Y_REGNUM) * SPARC_INTREG_SIZE
-	  - DUMMY_STACK_REG_BUF_SIZE;
-#endif
-      frame_addr = fi->bottom ?
-	fi->bottom : read_sp ();
+      else
+	for (regnum = Y_REGNUM; regnum < NUM_REGS; regnum++)
+	  saved_regs_addr[regnum] =
+	    frame_addr + (regnum - Y_REGNUM) * SPARC_INTREG_SIZE
+	    - DUMMY_STACK_REG_BUF_SIZE;
+
+      frame_addr = fi->extra_info->bottom ?
+	fi->extra_info->bottom : read_sp ();
     }
-  else if (fi->flat)
+  else if (fi->extra_info->flat)
     {
       CORE_ADDR func_start;
       find_pc_partial_function (fi->pc, NULL, &func_start, NULL);
       examine_prologue (func_start, 0, fi, saved_regs_addr);
 
       /* Flat register window frame.  */
-      saved_regs_addr->regs[RP_REGNUM] = fi->pc_addr;
-      saved_regs_addr->regs[I7_REGNUM] = fi->fp_addr;
+      saved_regs_addr[RP_REGNUM] = fi->extra_info->pc_addr;
+      saved_regs_addr[I7_REGNUM] = fi->extra_info->fp_addr;
     }
   else
     {
       /* Normal frame.  Just Local and In registers */
-      frame_addr = fi->bottom ?
-	fi->bottom : read_sp ();
+      frame_addr = fi->extra_info->bottom ?
+	fi->extra_info->bottom : read_sp ();
       for (regnum = L0_REGNUM; regnum < L0_REGNUM + 8; regnum++)
-	saved_regs_addr->regs[regnum] =
+	saved_regs_addr[regnum] =
 	  (frame_addr + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE
 	   + FRAME_SAVED_L0);
       for (regnum = I0_REGNUM; regnum < I0_REGNUM + 8; regnum++)
-	saved_regs_addr->regs[regnum] =
+	saved_regs_addr[regnum] =
 	  (frame_addr + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE
 	   + FRAME_SAVED_I0);
     }
   if (fi->next)
     {
-      if (fi->flat)
+      if (fi->extra_info->flat)
 	{
-	  saved_regs_addr->regs[O7_REGNUM] = fi->pc_addr;
+	  saved_regs_addr[O7_REGNUM] = fi->extra_info->pc_addr;
 	}
       else
 	{
 	  /* Pull off either the next frame pointer or the stack pointer */
 	  CORE_ADDR next_next_frame_addr =
-	  (fi->next->bottom ?
-	   fi->next->bottom :
-	   read_sp ());
+	  (fi->next->extra_info->bottom ?
+	   fi->next->extra_info->bottom : read_sp ());
 	  for (regnum = O0_REGNUM; regnum < O0_REGNUM + 8; regnum++)
-	    saved_regs_addr->regs[regnum] =
+	    saved_regs_addr[regnum] =
 	      (next_next_frame_addr
 	       + (regnum - O0_REGNUM) * SPARC_INTREG_SIZE
 	       + FRAME_SAVED_I0);
@@ -1067,7 +1162,7 @@ sparc_frame_find_saved_regs (fi, saved_regs_addr)
     }
   /* Otherwise, whatever we would get from ptrace(GETREGS) is accurate */
   /* FIXME -- should this adjust for the sparc64 offset? */
-  saved_regs_addr->regs[SP_REGNUM] = FRAME_FP (fi);
+  saved_regs_addr[SP_REGNUM] = FRAME_FP (fi);
 }
 
 /* Discard from the stack the innermost frame, restoring all saved registers.
@@ -1089,82 +1184,87 @@ sparc_pop_frame ()
 {
   register struct frame_info *frame = get_current_frame ();
   register CORE_ADDR pc;
-  struct frame_saved_regs fsr;
-  char raw_buffer[REGISTER_BYTES];
+  CORE_ADDR *fsr;
+  char *raw_buffer;
   int regnum;
 
-  sparc_frame_find_saved_regs (frame, &fsr);
-  if (FP0_REGNUM >= 0)
+  fsr = alloca (NUM_REGS * sizeof (CORE_ADDR));
+  raw_buffer = alloca (REGISTER_BYTES);
+  sparc_frame_find_saved_regs (frame, &fsr[0]);
+  if (SPARC_HAS_FPU)
     {
-      if (fsr.regs[FP0_REGNUM])
+      if (fsr[FP0_REGNUM])
 	{
-	  read_memory (fsr.regs[FP0_REGNUM], raw_buffer, FP_REGISTER_BYTES);
+	  read_memory (fsr[FP0_REGNUM], raw_buffer, FP_REGISTER_BYTES);
 	  write_register_bytes (REGISTER_BYTE (FP0_REGNUM),
 				raw_buffer, FP_REGISTER_BYTES);
 	}
-#ifndef GDB_TARGET_IS_SPARC64
-      if (fsr.regs[FPS_REGNUM])
-	{
-	  read_memory (fsr.regs[FPS_REGNUM], raw_buffer, 4);
-	  write_register_bytes (REGISTER_BYTE (FPS_REGNUM), raw_buffer, 4);
-	}
-      if (fsr.regs[CPS_REGNUM])
+      if (!(GDB_TARGET_IS_SPARC64))
 	{
-	  read_memory (fsr.regs[CPS_REGNUM], raw_buffer, 4);
-	  write_register_bytes (REGISTER_BYTE (CPS_REGNUM), raw_buffer, 4);
+	  if (fsr[FPS_REGNUM])
+	    {
+	      read_memory (fsr[FPS_REGNUM], raw_buffer, SPARC_INTREG_SIZE);
+	      write_register_gen (FPS_REGNUM, raw_buffer);
+	    }
+	  if (fsr[CPS_REGNUM])
+	    {
+	      read_memory (fsr[CPS_REGNUM], raw_buffer, SPARC_INTREG_SIZE);
+	      write_register_gen (CPS_REGNUM, raw_buffer);
+	    }
 	}
-#endif
     }
-  if (fsr.regs[G1_REGNUM])
+  if (fsr[G1_REGNUM])
     {
-      read_memory (fsr.regs[G1_REGNUM], raw_buffer, 7 * SPARC_INTREG_SIZE);
+      read_memory (fsr[G1_REGNUM], raw_buffer, 7 * SPARC_INTREG_SIZE);
       write_register_bytes (REGISTER_BYTE (G1_REGNUM), raw_buffer,
 			    7 * SPARC_INTREG_SIZE);
     }
 
-  if (frame->flat)
+  if (frame->extra_info->flat)
     {
       /* Each register might or might not have been saved, need to test
          individually.  */
       for (regnum = L0_REGNUM; regnum < L0_REGNUM + 8; ++regnum)
-	if (fsr.regs[regnum])
-	  write_register (regnum, read_memory_integer (fsr.regs[regnum],
+	if (fsr[regnum])
+	  write_register (regnum, read_memory_integer (fsr[regnum],
 						       SPARC_INTREG_SIZE));
       for (regnum = I0_REGNUM; regnum < I0_REGNUM + 8; ++regnum)
-	if (fsr.regs[regnum])
-	  write_register (regnum, read_memory_integer (fsr.regs[regnum],
+	if (fsr[regnum])
+	  write_register (regnum, read_memory_integer (fsr[regnum],
 						       SPARC_INTREG_SIZE));
 
       /* Handle all outs except stack pointer (o0-o5; o7).  */
       for (regnum = O0_REGNUM; regnum < O0_REGNUM + 6; ++regnum)
-	if (fsr.regs[regnum])
-	  write_register (regnum, read_memory_integer (fsr.regs[regnum],
+	if (fsr[regnum])
+	  write_register (regnum, read_memory_integer (fsr[regnum],
 						       SPARC_INTREG_SIZE));
-      if (fsr.regs[O0_REGNUM + 7])
+      if (fsr[O0_REGNUM + 7])
 	write_register (O0_REGNUM + 7,
-			read_memory_integer (fsr.regs[O0_REGNUM + 7],
+			read_memory_integer (fsr[O0_REGNUM + 7],
 					     SPARC_INTREG_SIZE));
 
       write_sp (frame->frame);
     }
-  else if (fsr.regs[I0_REGNUM])
+  else if (fsr[I0_REGNUM])
     {
       CORE_ADDR sp;
 
-      char reg_temp[REGISTER_BYTES];
+      char *reg_temp;
+
+      reg_temp = alloca (REGISTER_BYTES);
 
-      read_memory (fsr.regs[I0_REGNUM], raw_buffer, 8 * SPARC_INTREG_SIZE);
+      read_memory (fsr[I0_REGNUM], raw_buffer, 8 * SPARC_INTREG_SIZE);
 
       /* Get the ins and locals which we are about to restore.  Just
          moving the stack pointer is all that is really needed, except
          store_inferior_registers is then going to write the ins and
          locals from the registers array, so we need to muck with the
          registers array.  */
-      sp = fsr.regs[SP_REGNUM];
-#ifdef GDB_TARGET_IS_SPARC64
-      if (sp & 1)
+      sp = fsr[SP_REGNUM];
+ 
+      if (GDB_TARGET_IS_SPARC64 && (sp & 1))
 	sp += 2047;
-#endif
+
       read_memory (sp, reg_temp, SPARC_INTREG_SIZE * 16);
 
       /* Restore the out registers.
@@ -1175,34 +1275,42 @@ sparc_pop_frame ()
       write_register_bytes (REGISTER_BYTE (L0_REGNUM), reg_temp,
 			    SPARC_INTREG_SIZE * 16);
     }
-#ifndef GDB_TARGET_IS_SPARC64
-  if (fsr.regs[PS_REGNUM])
-    write_register (PS_REGNUM, read_memory_integer (fsr.regs[PS_REGNUM], 4));
-#endif
-  if (fsr.regs[Y_REGNUM])
-    write_register (Y_REGNUM, read_memory_integer (fsr.regs[Y_REGNUM], REGISTER_RAW_SIZE (Y_REGNUM)));
-  if (fsr.regs[PC_REGNUM])
+
+  if (!(GDB_TARGET_IS_SPARC64))
+    if (fsr[PS_REGNUM])
+      write_register (PS_REGNUM, 
+		      read_memory_integer (fsr[PS_REGNUM], 
+					   REGISTER_RAW_SIZE (PS_REGNUM)));
+
+  if (fsr[Y_REGNUM])
+    write_register (Y_REGNUM, 
+		    read_memory_integer (fsr[Y_REGNUM], 
+					 REGISTER_RAW_SIZE (Y_REGNUM)));
+  if (fsr[PC_REGNUM])
     {
       /* Explicitly specified PC (and maybe NPC) -- just restore them. */
-      write_register (PC_REGNUM, read_memory_integer (fsr.regs[PC_REGNUM],
-					    REGISTER_RAW_SIZE (PC_REGNUM)));
-      if (fsr.regs[NPC_REGNUM])
+      write_register (PC_REGNUM, 
+		      read_memory_integer (fsr[PC_REGNUM],
+					   REGISTER_RAW_SIZE (PC_REGNUM)));
+      if (fsr[NPC_REGNUM])
 	write_register (NPC_REGNUM,
-			read_memory_integer (fsr.regs[NPC_REGNUM],
-					   REGISTER_RAW_SIZE (NPC_REGNUM)));
+			read_memory_integer (fsr[NPC_REGNUM],
+					     REGISTER_RAW_SIZE (NPC_REGNUM)));
     }
-  else if (frame->flat)
+  else if (frame->extra_info->flat)
     {
-      if (frame->pc_addr)
+      if (frame->extra_info->pc_addr)
 	pc = PC_ADJUST ((CORE_ADDR)
-			read_memory_integer (frame->pc_addr,
+			read_memory_integer (frame->extra_info->pc_addr,
 					     REGISTER_RAW_SIZE (PC_REGNUM)));
       else
 	{
 	  /* I think this happens only in the innermost frame, if so then
 	     it is a complicated way of saying
 	     "pc = read_register (O7_REGNUM);".  */
-	  char buf[MAX_REGISTER_RAW_SIZE];
+	  char *buf;
+
+	  buf = alloca (MAX_REGISTER_RAW_SIZE);
 	  get_saved_register (buf, 0, 0, frame, O7_REGNUM, 0);
 	  pc = PC_ADJUST (extract_address
 			  (buf, REGISTER_RAW_SIZE (O7_REGNUM)));
@@ -1211,10 +1319,10 @@ sparc_pop_frame ()
       write_register (PC_REGNUM, pc);
       write_register (NPC_REGNUM, pc + 4);
     }
-  else if (fsr.regs[I7_REGNUM])
+  else if (fsr[I7_REGNUM])
     {
       /* Return address in %i7 -- adjust it, then restore PC and NPC from it */
-      pc = PC_ADJUST ((CORE_ADDR) read_memory_integer (fsr.regs[I7_REGNUM],
+      pc = PC_ADJUST ((CORE_ADDR) read_memory_integer (fsr[I7_REGNUM],
 						       SPARC_INTREG_SIZE));
       write_register (PC_REGNUM, pc);
       write_register (NPC_REGNUM, pc + 4);
@@ -1333,27 +1441,122 @@ void
 supply_gregset (gregsetp)
      prgregset_t *gregsetp;
 {
-  register int regi;
-  register prgreg_t *regp = (prgreg_t *) gregsetp;
-  static char zerobuf[MAX_REGISTER_RAW_SIZE] =
-  {0};
+  prgreg_t *regp = (prgreg_t *) gregsetp;
+  int regi, offset = 0;
+
+  /* If the host is 64-bit sparc, but the target is 32-bit sparc, 
+     then the gregset may contain 64-bit ints while supply_register
+     is expecting 32-bit ints.  Compensate.  */
+  if (sizeof (regp[0]) == 8 && SPARC_INTREG_SIZE == 4)
+    offset = 4;
 
   /* GDB register numbers for Gn, On, Ln, In all match /proc reg numbers.  */
+  /* FIXME MVS: assumes the order of the first 32 elements... */
   for (regi = G0_REGNUM; regi <= I7_REGNUM; regi++)
     {
-      supply_register (regi, (char *) (regp + regi));
+      supply_register (regi, ((char *) (regp + regi)) + offset);
     }
 
   /* These require a bit more care.  */
-  supply_register (PS_REGNUM, (char *) (regp + R_PS));
-  supply_register (PC_REGNUM, (char *) (regp + R_PC));
-  supply_register (NPC_REGNUM, (char *) (regp + R_nPC));
-  supply_register (Y_REGNUM, (char *) (regp + R_Y));
+  supply_register (PC_REGNUM, ((char *) (regp + R_PC)) + offset);
+  supply_register (NPC_REGNUM, ((char *) (regp + R_nPC)) + offset);
+  supply_register (Y_REGNUM, ((char *) (regp + R_Y)) + offset);
+
+  if (GDB_TARGET_IS_SPARC64)
+    {
+#ifdef R_CCR
+      supply_register (CCR_REGNUM, ((char *) (regp + R_CCR)) + offset);
+#else
+      supply_register (CCR_REGNUM, NULL);
+#endif
+#ifdef R_FPRS
+      supply_register (FPRS_REGNUM, ((char *) (regp + R_FPRS)) + offset);
+#else
+      supply_register (FPRS_REGNUM, NULL);
+#endif
+#ifdef R_ASI
+      supply_register (ASI_REGNUM, ((char *) (regp + R_ASI)) + offset);
+#else
+      supply_register (ASI_REGNUM, NULL);
+#endif
+    }
+  else	/* sparc32 */
+    {
+#ifdef R_PS
+      supply_register (PS_REGNUM, ((char *) (regp + R_PS)) + offset);
+#else
+      supply_register (PS_REGNUM, NULL);
+#endif
+
+      /* For 64-bit hosts, R_WIM and R_TBR may not be defined.
+	 Steal R_ASI and R_FPRS, and hope for the best!  */
+
+#if !defined (R_WIM) && defined (R_ASI)
+#define R_WIM R_ASI
+#endif
+
+#if !defined (R_TBR) && defined (R_FPRS)
+#define R_TBR R_FPRS
+#endif
+
+#if defined (R_WIM)
+      supply_register (WIM_REGNUM, ((char *) (regp + R_WIM)) + offset);
+#else
+      supply_register (WIM_REGNUM, NULL);
+#endif
+
+#if defined (R_TBR)
+      supply_register (TBR_REGNUM, ((char *) (regp + R_TBR)) + offset);
+#else
+      supply_register (TBR_REGNUM, NULL);
+#endif
+    }
 
   /* Fill inaccessible registers with zero.  */
-  supply_register (WIM_REGNUM, zerobuf);
-  supply_register (TBR_REGNUM, zerobuf);
-  supply_register (CPS_REGNUM, zerobuf);
+  if (GDB_TARGET_IS_SPARC64)
+    {
+      /*
+       * don't know how to get value of any of the following:
+       */
+      supply_register (VER_REGNUM, NULL);
+      supply_register (TICK_REGNUM, NULL);
+      supply_register (PIL_REGNUM, NULL);
+      supply_register (PSTATE_REGNUM, NULL);
+      supply_register (TSTATE_REGNUM, NULL);
+      supply_register (TBA_REGNUM, NULL);
+      supply_register (TL_REGNUM, NULL);
+      supply_register (TT_REGNUM, NULL);
+      supply_register (TPC_REGNUM, NULL);
+      supply_register (TNPC_REGNUM, NULL);
+      supply_register (WSTATE_REGNUM, NULL);
+      supply_register (CWP_REGNUM, NULL);
+      supply_register (CANSAVE_REGNUM, NULL);
+      supply_register (CANRESTORE_REGNUM, NULL);
+      supply_register (CLEANWIN_REGNUM, NULL);
+      supply_register (OTHERWIN_REGNUM, NULL);
+      supply_register (ASR16_REGNUM, NULL);
+      supply_register (ASR17_REGNUM, NULL);
+      supply_register (ASR18_REGNUM, NULL);
+      supply_register (ASR19_REGNUM, NULL);
+      supply_register (ASR20_REGNUM, NULL);
+      supply_register (ASR21_REGNUM, NULL);
+      supply_register (ASR22_REGNUM, NULL);
+      supply_register (ASR23_REGNUM, NULL);
+      supply_register (ASR24_REGNUM, NULL);
+      supply_register (ASR25_REGNUM, NULL);
+      supply_register (ASR26_REGNUM, NULL);
+      supply_register (ASR27_REGNUM, NULL);
+      supply_register (ASR28_REGNUM, NULL);
+      supply_register (ASR29_REGNUM, NULL);
+      supply_register (ASR30_REGNUM, NULL);
+      supply_register (ASR31_REGNUM, NULL);
+      supply_register (ICC_REGNUM, NULL);
+      supply_register (XCC_REGNUM, NULL);
+    }
+  else
+    {
+      supply_register (CPS_REGNUM, NULL);
+    }
 }
 
 void
@@ -1361,31 +1564,76 @@ fill_gregset (gregsetp, regno)
      prgregset_t *gregsetp;
      int regno;
 {
-  int regi;
-  register prgreg_t *regp = (prgreg_t *) gregsetp;
+  prgreg_t *regp = (prgreg_t *) gregsetp;
+  int regi, offset = 0;
+
+  /* If the host is 64-bit sparc, but the target is 32-bit sparc, 
+     then the gregset may contain 64-bit ints while supply_register
+     is expecting 32-bit ints.  Compensate.  */
+  if (sizeof (regp[0]) == 8 && SPARC_INTREG_SIZE == 4)
+    offset = 4;
 
   for (regi = 0; regi <= R_I7; regi++)
-    {
-      if ((regno == -1) || (regno == regi))
-	{
-	  *(regp + regi) = *(int *) &registers[REGISTER_BYTE (regi)];
-	}
-    }
-  if ((regno == -1) || (regno == PS_REGNUM))
-    {
-      *(regp + R_PS) = *(int *) &registers[REGISTER_BYTE (PS_REGNUM)];
-    }
+    if ((regno == -1) || (regno == regi))
+      read_register_gen (regi, (char *) (regp + regi) + offset);
+
   if ((regno == -1) || (regno == PC_REGNUM))
-    {
-      *(regp + R_PC) = *(int *) &registers[REGISTER_BYTE (PC_REGNUM)];
-    }
+    read_register_gen (PC_REGNUM, (char *) (regp + R_PC) + offset);
+
   if ((regno == -1) || (regno == NPC_REGNUM))
+    read_register_gen (NPC_REGNUM, (char *) (regp + R_nPC) + offset);
+
+  if ((regno == -1) || (regno == Y_REGNUM))
+    read_register_gen (Y_REGNUM, (char *) (regp + R_Y) + offset);
+
+  if (GDB_TARGET_IS_SPARC64)
     {
-      *(regp + R_nPC) = *(int *) &registers[REGISTER_BYTE (NPC_REGNUM)];
+#ifdef R_CCR
+      if (regno == -1 || regno == CCR_REGNUM)
+	read_register_gen (CCR_REGNUM, ((char *) (regp + R_CCR)) + offset);
+#endif
+#ifdef R_FPRS
+      if (regno == -1 || regno == FPRS_REGNUM)
+	read_register_gen (FPRS_REGNUM, ((char *) (regp + R_FPRS)) + offset);
+#endif
+#ifdef R_ASI
+      if (regno == -1 || regno == ASI_REGNUM)
+	read_register_gen (ASI_REGNUM, ((char *) (regp + R_ASI)) + offset);
+#endif
     }
-  if ((regno == -1) || (regno == Y_REGNUM))
+  else /* sparc32 */
     {
-      *(regp + R_Y) = *(int *) &registers[REGISTER_BYTE (Y_REGNUM)];
+#ifdef R_PS
+      if (regno == -1 || regno == PS_REGNUM)
+	read_register_gen (PS_REGNUM, ((char *) (regp + R_PS)) + offset);
+#endif
+
+      /* For 64-bit hosts, R_WIM and R_TBR may not be defined.
+	 Steal R_ASI and R_FPRS, and hope for the best!  */
+
+#if !defined (R_WIM) && defined (R_ASI)
+#define R_WIM R_ASI
+#endif
+
+#if !defined (R_TBR) && defined (R_FPRS)
+#define R_TBR R_FPRS
+#endif
+
+#if defined (R_WIM)
+      if (regno == -1 || regno == WIM_REGNUM)
+	read_register_gen (WIM_REGNUM, ((char *) (regp + R_WIM)) + offset);
+#else
+      if (regno == -1 || regno == WIM_REGNUM)
+	read_register_gen (WIM_REGNUM, NULL);
+#endif
+
+#if defined (R_TBR)
+      if (regno == -1 || regno == TBR_REGNUM)
+	read_register_gen (TBR_REGNUM, ((char *) (regp + R_TBR)) + offset);
+#else
+      if (regno == -1 || regno == TBR_REGNUM)
+	read_register_gen (TBR_REGNUM, NULL);
+#endif
     }
 }
 
@@ -1400,7 +1648,7 @@ supply_fpregset (fpregsetp)
   register int regi;
   char *from;
 
-  if (FP0_REGNUM < 0)
+  if (!SPARC_HAS_FPU)
     return;
 
   for (regi = FP0_REGNUM; regi < FP_MAX_REGNUM; regi++)
@@ -1408,14 +1656,29 @@ supply_fpregset (fpregsetp)
       from = (char *) &fpregsetp->pr_fr.pr_regs[regi - FP0_REGNUM];
       supply_register (regi, from);
     }
-  supply_register (FPS_REGNUM, (char *) &(fpregsetp->pr_fsr));
+
+  if (GDB_TARGET_IS_SPARC64)
+    {
+      /*
+       * don't know how to get value of the following.  
+       */
+      supply_register (FSR_REGNUM, NULL);	/* zero it out for now */
+      supply_register (FCC0_REGNUM, NULL);
+      supply_register (FCC1_REGNUM, NULL); /* don't know how to get value */
+      supply_register (FCC2_REGNUM, NULL); /* don't know how to get value */
+      supply_register (FCC3_REGNUM, NULL); /* don't know how to get value */
+    }
+  else
+    {
+      supply_register (FPS_REGNUM, (char *) &(fpregsetp->pr_fsr));
+    }
 }
 
 /*  Given a pointer to a floating point register set in /proc format
    (fpregset_t *), update the register specified by REGNO from gdb's idea
    of the current floating point register set.  If REGNO is -1, update
    them all. */
-/* ??? This will probably need some changes for sparc64.  */
+/* This will probably need some changes for sparc64.  */
 
 void
 fill_fpregset (fpregsetp, regno)
@@ -1426,7 +1689,7 @@ fill_fpregset (fpregsetp, regno)
   char *to;
   char *from;
 
-  if (FP0_REGNUM < 0)
+  if (!SPARC_HAS_FPU)
     return;
 
   for (regi = FP0_REGNUM; regi < FP_MAX_REGNUM; regi++)
@@ -1438,10 +1701,14 @@ fill_fpregset (fpregsetp, regno)
 	  memcpy (to, from, REGISTER_RAW_SIZE (regi));
 	}
     }
-  if ((regno == -1) || (regno == FPS_REGNUM))
-    {
-      fpregsetp->pr_fsr = *(int *) &registers[REGISTER_BYTE (FPS_REGNUM)];
-    }
+
+  if (!(GDB_TARGET_IS_SPARC64)) /* FIXME: does Sparc64 have this register? */
+    if ((regno == -1) || (regno == FPS_REGNUM))
+      {
+	from = (char *)&registers[REGISTER_BYTE (FPS_REGNUM)];
+	to = (char *) &fpregsetp->pr_fsr;
+	memcpy (to, from, REGISTER_RAW_SIZE (FPS_REGNUM));
+      }
 }
 
 #endif /* USE_PROC_FS */
@@ -1505,7 +1772,7 @@ sunpro_static_transform_name (name)
 /* Utilities for printing registers.
    Page numbers refer to the SPARC Architecture Manual.  */
 
-static void dump_ccreg PARAMS ((char *, int));
+static void dump_ccreg (char *, int);
 
 static void
 dump_ccreg (reg, val)
@@ -1517,8 +1784,7 @@ dump_ccreg (reg, val)
 		     val & 8 ? "N" : "NN",
 		     val & 4 ? "Z" : "NZ",
 		     val & 2 ? "O" : "NO",
-		     val & 1 ? "C" : "NC"
-    );
+		     val & 1 ? "C" : "NC");
 }
 
 static char *
@@ -1624,111 +1890,116 @@ sparc_print_register_hook (regno)
   val = read_register (regno);
 
   /* pages 40 - 60 */
-  switch (regno)
-    {
-#ifdef GDB_TARGET_IS_SPARC64
-    case CCR_REGNUM:
-      printf_unfiltered ("\t");
-      dump_ccreg ("xcc", val >> 4);
-      printf_unfiltered (", ");
-      dump_ccreg ("icc", val & 15);
-      break;
-    case FPRS_REGNUM:
-      printf ("\tfef:%d, du:%d, dl:%d",
-	      BITS (2, 1), BITS (1, 1), BITS (0, 1));
-      break;
-    case FSR_REGNUM:
+  if (GDB_TARGET_IS_SPARC64)
+    switch (regno)
       {
-	static char *fcc[4] =
-	{"=", "<", ">", "?"};
-	static char *rd[4] =
-	{"N", "0", "+", "-"};
-	/* Long, yes, but I'd rather leave it as is and use a wide screen.  */
-	printf ("\t0:%s, 1:%s, 2:%s, 3:%s, rd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, aexc:%d, cexc:%d",
-		fcc[BITS (10, 3)], fcc[BITS (32, 3)],
-		fcc[BITS (34, 3)], fcc[BITS (36, 3)],
-		rd[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7),
-		BITS (14, 7), BITS (13, 1), BITS (5, 31), BITS (0, 31));
+      case CCR_REGNUM:
+	printf_unfiltered ("\t");
+	dump_ccreg ("xcc", val >> 4);
+	printf_unfiltered (", ");
+	dump_ccreg ("icc", val & 15);
 	break;
-      }
-    case ASI_REGNUM:
-      {
-	char *asi = decode_asi (val);
-	if (asi != NULL)
-	  printf ("\t%s", asi);
+      case FPRS_REGNUM:
+	printf ("\tfef:%d, du:%d, dl:%d",
+		BITS (2, 1), BITS (1, 1), BITS (0, 1));
 	break;
-      }
-    case VER_REGNUM:
-      printf ("\tmanuf:%d, impl:%d, mask:%d, maxtl:%d, maxwin:%d",
-	      BITS (48, 0xffff), BITS (32, 0xffff),
-	      BITS (24, 0xff), BITS (8, 0xff), BITS (0, 31));
-      break;
-    case PSTATE_REGNUM:
-      {
-	static char *mm[4] =
-	{"tso", "pso", "rso", "?"};
-	printf ("\tcle:%d, tle:%d, mm:%s, red:%d, pef:%d, am:%d, priv:%d, ie:%d, ag:%d",
-		BITS (9, 1), BITS (8, 1), mm[BITS (6, 3)], BITS (5, 1),
-		BITS (4, 1), BITS (3, 1), BITS (2, 1), BITS (1, 1),
-		BITS (0, 1));
+      case FSR_REGNUM:
+	{
+	  static char *fcc[4] =
+	  {"=", "<", ">", "?"};
+	  static char *rd[4] =
+	  {"N", "0", "+", "-"};
+	  /* Long, but I'd rather leave it as is and use a wide screen.  */
+	  printf_filtered ("\t0:%s, 1:%s, 2:%s, 3:%s, rd:%s, tem:%d, ",
+			   fcc[BITS (10, 3)], fcc[BITS (32, 3)],
+			   fcc[BITS (34, 3)], fcc[BITS (36, 3)],
+			   rd[BITS (30, 3)], BITS (23, 31));
+	  printf_filtered ("ns:%d, ver:%d, ftt:%d, qne:%d, aexc:%d, cexc:%d",
+			   BITS (22, 1), BITS (17, 7), BITS (14, 7), 
+			   BITS (13, 1), BITS (5, 31), BITS (0, 31));
+	  break;
+	}
+      case ASI_REGNUM:
+	{
+	  char *asi = decode_asi (val);
+	  if (asi != NULL)
+	    printf ("\t%s", asi);
+	  break;
+	}
+      case VER_REGNUM:
+	printf ("\tmanuf:%d, impl:%d, mask:%d, maxtl:%d, maxwin:%d",
+		BITS (48, 0xffff), BITS (32, 0xffff),
+		BITS (24, 0xff), BITS (8, 0xff), BITS (0, 31));
+	break;
+      case PSTATE_REGNUM:
+	{
+	  static char *mm[4] =
+	  {"tso", "pso", "rso", "?"};
+	  printf_filtered ("\tcle:%d, tle:%d, mm:%s, red:%d, ",
+			   BITS (9, 1), BITS (8, 1), 
+			   mm[BITS (6, 3)], BITS (5, 1));
+	  printf_filtered ("pef:%d, am:%d, priv:%d, ie:%d, ag:%d",
+			   BITS (4, 1), BITS (3, 1), BITS (2, 1), 
+			   BITS (1, 1), BITS (0, 1));
+	  break;
+	}
+      case TSTATE_REGNUM:
+	/* FIXME: print all 4? */
+	break;
+      case TT_REGNUM:
+	/* FIXME: print all 4? */
+	break;
+      case TPC_REGNUM:
+	/* FIXME: print all 4? */
+	break;
+      case TNPC_REGNUM:
+	/* FIXME: print all 4? */
+	break;
+      case WSTATE_REGNUM:
+	printf ("\tother:%d, normal:%d", BITS (3, 7), BITS (0, 7));
+	break;
+      case CWP_REGNUM:
+	printf ("\t%d", BITS (0, 31));
+	break;
+      case CANSAVE_REGNUM:
+	printf ("\t%-2d before spill", BITS (0, 31));
+	break;
+      case CANRESTORE_REGNUM:
+	printf ("\t%-2d before fill", BITS (0, 31));
+	break;
+      case CLEANWIN_REGNUM:
+	printf ("\t%-2d before clean", BITS (0, 31));
+	break;
+      case OTHERWIN_REGNUM:
+	printf ("\t%d", BITS (0, 31));
 	break;
       }
-    case TSTATE_REGNUM:
-      /* FIXME: print all 4? */
-      break;
-    case TT_REGNUM:
-      /* FIXME: print all 4? */
-      break;
-    case TPC_REGNUM:
-      /* FIXME: print all 4? */
-      break;
-    case TNPC_REGNUM:
-      /* FIXME: print all 4? */
-      break;
-    case WSTATE_REGNUM:
-      printf ("\tother:%d, normal:%d", BITS (3, 7), BITS (0, 7));
-      break;
-    case CWP_REGNUM:
-      printf ("\t%d", BITS (0, 31));
-      break;
-    case CANSAVE_REGNUM:
-      printf ("\t%-2d before spill", BITS (0, 31));
-      break;
-    case CANRESTORE_REGNUM:
-      printf ("\t%-2d before fill", BITS (0, 31));
-      break;
-    case CLEANWIN_REGNUM:
-      printf ("\t%-2d before clean", BITS (0, 31));
-      break;
-    case OTHERWIN_REGNUM:
-      printf ("\t%d", BITS (0, 31));
-      break;
-#else
-    case PS_REGNUM:
-      printf ("\ticc:%c%c%c%c, pil:%d, s:%d, ps:%d, et:%d, cwp:%d",
-	      BITS (23, 1) ? 'N' : '-', BITS (22, 1) ? 'Z' : '-',
-	      BITS (21, 1) ? 'V' : '-', BITS (20, 1) ? 'C' : '-',
-	      BITS (8, 15), BITS (7, 1), BITS (6, 1), BITS (5, 1),
-	      BITS (0, 31));
-      break;
-    case FPS_REGNUM:
+  else	/* Sparc32 */
+    switch (regno) 
       {
-	static char *fcc[4] =
-	{"=", "<", ">", "?"};
-	static char *rd[4] =
-	{"N", "0", "+", "-"};
-	/* Long, yes, but I'd rather leave it as is and use a wide screen.  */
-	printf ("\trd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, "
-		"fcc:%s, aexc:%d, cexc:%d",
-		rd[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7),
-		BITS (14, 7), BITS (13, 1), fcc[BITS (10, 3)], BITS (5, 31),
+      case PS_REGNUM:
+	printf ("\ticc:%c%c%c%c, pil:%d, s:%d, ps:%d, et:%d, cwp:%d",
+		BITS (23, 1) ? 'N' : '-', BITS (22, 1) ? 'Z' : '-',
+		BITS (21, 1) ? 'V' : '-', BITS (20, 1) ? 'C' : '-',
+		BITS (8, 15), BITS (7, 1), BITS (6, 1), BITS (5, 1),
 		BITS (0, 31));
 	break;
+      case FPS_REGNUM:
+	{
+	  static char *fcc[4] =
+	  {"=", "<", ">", "?"};
+	  static char *rd[4] =
+	  {"N", "0", "+", "-"};
+	  /* Long, but I'd rather leave it as is and use a wide screen.  */
+	  printf ("\trd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, "
+		  "fcc:%s, aexc:%d, cexc:%d",
+		  rd[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7),
+		  BITS (14, 7), BITS (13, 1), fcc[BITS (10, 3)], BITS (5, 31),
+		  BITS (0, 31));
+	  break;
+	}
       }
 
-#endif /* GDB_TARGET_IS_SPARC64 */
-    }
-
 #undef BITS
 }
 
@@ -1739,21 +2010,26 @@ gdb_print_insn_sparc (memaddr, info)
 {
   /* It's necessary to override mach again because print_insn messes it up. */
   info->mach = TARGET_ARCHITECTURE->mach;
+#if 1
+  /* Selects sparc/sparclite/sparclet/sparc64 */
+  tm_print_insn_info.mach = gdbarch_tdep (current_gdbarch) -> print_insn_mach;
+#endif
   return print_insn_sparc (memaddr, info);
 }
 
 /* The SPARC passes the arguments on the stack; arguments smaller
-   than an int are promoted to an int.  */
+   than an int are promoted to an int.  The first 6 words worth of 
+   args are also passed in registers o0 - o5.  */
 
 CORE_ADDR
-sparc_push_arguments (nargs, args, sp, struct_return, struct_addr)
+sparc32_push_arguments (nargs, args, sp, struct_return, struct_addr)
      int nargs;
      value_ptr *args;
      CORE_ADDR sp;
      int struct_return;
      CORE_ADDR struct_addr;
 {
-  int i;
+  int i, j, oregnum;
   int accumulate_size = 0;
   struct sparc_arg
     {
@@ -1762,7 +2038,7 @@ sparc_push_arguments (nargs, args, sp, struct_return, struct_addr)
       int offset;
     };
   struct sparc_arg *sparc_args =
-  (struct sparc_arg *) alloca (nargs * sizeof (struct sparc_arg));
+    (struct sparc_arg *) alloca (nargs * sizeof (struct sparc_arg));
   struct sparc_arg *m_arg;
 
   /* Promote arguments if necessary, and calculate their stack offsets
@@ -1799,8 +2075,16 @@ sparc_push_arguments (nargs, args, sp, struct_return, struct_addr)
   sp = ((sp - accumulate_size) & ~7) + CALL_DUMMY_STACK_ADJUST;
 
   /* `Push' arguments on the stack.  */
-  for (i = nargs; m_arg--, --i >= 0;)
-    write_memory (sp + m_arg->offset, m_arg->contents, m_arg->len);
+  for (i = 0, oregnum = 0, m_arg = sparc_args; 
+       i < nargs;
+       i++, m_arg++)
+    {
+      write_memory (sp + m_arg->offset, m_arg->contents, m_arg->len);
+      for (j = 0; 
+	   j < m_arg->len && oregnum < 6; 
+	   j += SPARC_INTREG_SIZE, oregnum++)
+	write_register_gen (O0_REGNUM + oregnum, m_arg->contents + j);
+    }
 
   return sp;
 }
@@ -1811,7 +2095,7 @@ sparc_push_arguments (nargs, args, sp, struct_return, struct_addr)
    into VALBUF.  */
 
 void
-sparc_extract_return_value (type, regbuf, valbuf)
+sparc32_extract_return_value (type, regbuf, valbuf)
      struct type *type;
      char *regbuf;
      char *valbuf;
@@ -1842,7 +2126,9 @@ sparc_store_return_value (type, valbuf)
      char *valbuf;
 {
   int regno;
-  char buffer[MAX_REGISTER_RAW_SIZE];
+  char *buffer;
+
+  buffer = alloca(MAX_REGISTER_RAW_SIZE);
 
   if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU)
     /* Floating-point values are returned in the register pair */
@@ -1855,16 +2141,28 @@ sparc_store_return_value (type, valbuf)
   /* Add leading zeros to the value. */
   if (TYPE_LENGTH (type) < REGISTER_RAW_SIZE (regno))
     {
-      bzero (buffer, REGISTER_RAW_SIZE (regno));
+      memset (buffer, 0, REGISTER_RAW_SIZE (regno));
       memcpy (buffer + REGISTER_RAW_SIZE (regno) - TYPE_LENGTH (type), valbuf,
 	      TYPE_LENGTH (type));
-      write_register_bytes (REGISTER_BYTE (regno), buffer,
-			    REGISTER_RAW_SIZE (regno));
+      write_register_gen (regno, buffer);
     }
   else
     write_register_bytes (REGISTER_BYTE (regno), valbuf, TYPE_LENGTH (type));
 }
 
+extern void
+sparclet_store_return_value (struct type *type, char *valbuf)
+{
+  /* Other values are returned in register %o0.  */
+  write_register_bytes (REGISTER_BYTE (O0_REGNUM), valbuf,
+			TYPE_LENGTH (type));
+}
+
+
+#ifndef CALL_DUMMY_CALL_OFFSET
+#define CALL_DUMMY_CALL_OFFSET \
+     (gdbarch_tdep (current_gdbarch)->call_dummy_call_offset)
+#endif /* CALL_DUMMY_CALL_OFFSET */
 
 /* Insert the function address into a call dummy instruction sequence
    stored at DUMMY.
@@ -1900,17 +2198,19 @@ sparc_fix_call_dummy (dummy, pc, fun, value_type, using_gcc)
     store_unsigned_integer (dummy + CALL_DUMMY_CALL_OFFSET + 8, 4,
 			    TYPE_LENGTH (value_type) & 0x1fff);
 
-#ifndef GDB_TARGET_IS_SPARC64
-  /* If this is not a simulator target, change the first four instructions
-     of the call dummy to NOPs.  Those instructions include a 'save'
-     instruction and are designed to work around problems with register
-     window flushing in the simulator. */
-  if (strcmp (target_shortname, "sim") != 0)
+  if (!(GDB_TARGET_IS_SPARC64))
     {
-      for (i = 0; i < 4; i++)
-	store_unsigned_integer (dummy + (i * 4), 4, 0x01000000);
+      /* If this is not a simulator target, change the first four
+	 instructions of the call dummy to NOPs.  Those instructions
+	 include a 'save' instruction and are designed to work around
+	 problems with register window flushing in the simulator. */
+      
+      if (strcmp (target_shortname, "sim") != 0)
+	{
+	  for (i = 0; i < 4; i++)
+	    store_unsigned_integer (dummy + (i * 4), 4, 0x01000000);
+	}
     }
-#endif
 
   /* If this is a bi-endian target, GDB has written the call dummy
      in little-endian order.  We must byte-swap it back to big-endian. */
@@ -1955,21 +2255,29 @@ sparc_target_architecture_hook (ap)
 }
 
 
+/*
+ * Module "constructor" function. 
+ */
+
+static struct gdbarch * sparc_gdbarch_init (struct gdbarch_info info,
+					    struct gdbarch_list *arches);
+
 void
 _initialize_sparc_tdep ()
 {
+  /* Hook us into the gdbarch mechanism.  */
+  register_gdbarch_init (bfd_arch_sparc, sparc_gdbarch_init);
+
   tm_print_insn = gdb_print_insn_sparc;
   tm_print_insn_info.mach = TM_PRINT_INSN_MACH;		/* Selects sparc/sparclite */
   target_architecture_hook = sparc_target_architecture_hook;
 }
 
+/* Compensate for stack bias. Note that we currently don't handle
+   mixed 32/64 bit code. */
 
-#ifdef GDB_TARGET_IS_SPARC64
-
-/* Compensate for stack bias. Note that we currently don't handle mixed
-   32/64 bit code. */
 CORE_ADDR
-sparc64_read_sp ()
+sparc64_read_sp (void)
 {
   CORE_ADDR sp = read_register (SP_REGNUM);
 
@@ -1979,7 +2287,7 @@ sparc64_read_sp ()
 }
 
 CORE_ADDR
-sparc64_read_fp ()
+sparc64_read_fp (void)
 {
   CORE_ADDR fp = read_register (FP_REGNUM);
 
@@ -2010,35 +2318,47 @@ sparc64_write_fp (val)
     write_register (FP_REGNUM, val);
 }
 
-/* The SPARC 64 ABI passes floating-point arguments in FP0-31. They are
-   also copied onto the stack in the correct places. */
+/* The SPARC 64 ABI passes floating-point arguments in FP0 to FP31,
+   and all other arguments in O0 to O5.  They are also copied onto
+   the stack in the correct places.  Apparently (empirically), 
+   structs of less than 16 bytes are passed member-by-member in
+   separate registers, but I am unable to figure out the algorithm.
+   Some members go in floating point regs, but I don't know which.
+
+   FIXME: Handle small structs (less than 16 bytes containing floats).
+
+   The counting regimen for using both integer and FP registers
+   for argument passing is rather odd -- a single counter is used
+   for both; this means that if the arguments alternate between
+   int and float, we will waste every other register of both types.  */
 
 CORE_ADDR
-sp64_push_arguments (nargs, args, sp, struct_return, struct_retaddr)
+sparc64_push_arguments (nargs, args, sp, struct_return, struct_retaddr)
      int nargs;
      value_ptr *args;
      CORE_ADDR sp;
-     unsigned char struct_return;
+     int struct_return;
      CORE_ADDR struct_retaddr;
 {
-  int x;
-  int regnum = 0;
+  int i, j, register_counter = 0;
   CORE_ADDR tempsp;
+  struct type *sparc_intreg_type = 
+    TYPE_LENGTH (builtin_type_long) == SPARC_INTREG_SIZE ?
+    builtin_type_long : builtin_type_long_long;
 
-  sp = (sp & ~(((unsigned long) TYPE_LENGTH (builtin_type_long)) - 1UL));
+  sp = (sp & ~(((unsigned long) SPARC_INTREG_SIZE) - 1UL));
 
   /* Figure out how much space we'll need. */
-  for (x = nargs - 1; x >= 0; x--)
+  for (i = nargs - 1; i >= 0; i--)
     {
-      int len = TYPE_LENGTH (check_typedef (VALUE_TYPE (args[x])));
-      value_ptr copyarg = args[x];
+      int len = TYPE_LENGTH (check_typedef (VALUE_TYPE (args[i])));
+      value_ptr copyarg = args[i];
       int copylen = len;
 
-      /* This code is, of course, no longer correct. */
-      if (copylen < TYPE_LENGTH (builtin_type_long))
+      if (copylen < SPARC_INTREG_SIZE)
 	{
-	  copyarg = value_cast (builtin_type_long, copyarg);
-	  copylen = TYPE_LENGTH (builtin_type_long);
+	  copyarg = value_cast (sparc_intreg_type, copyarg);
+	  copylen = SPARC_INTREG_SIZE;
 	}
       sp -= copylen;
     }
@@ -2047,48 +2367,92 @@ sp64_push_arguments (nargs, args, sp, struct_return, struct_retaddr)
   sp = sp & ~7;
   tempsp = sp;
 
-  /* Now write the arguments onto the stack, while writing FP arguments
-     into the FP registers. */
-  for (x = 0; x < nargs; x++)
+  /* if STRUCT_RETURN, then first argument is the struct return location. */
+  if (struct_return)
+    write_register (O0_REGNUM + register_counter++, struct_retaddr);
+
+  /* Now write the arguments onto the stack, while writing FP
+     arguments into the FP registers, and other arguments into the
+     first six 'O' registers.  */
+
+  for (i = 0; i < nargs; i++)
     {
-      int len = TYPE_LENGTH (check_typedef (VALUE_TYPE (args[x])));
-      value_ptr copyarg = args[x];
+      int len = TYPE_LENGTH (check_typedef (VALUE_TYPE (args[i])));
+      value_ptr copyarg = args[i];
+      enum type_code typecode = TYPE_CODE (VALUE_TYPE (args[i]));
       int copylen = len;
 
-      /* This code is, of course, no longer correct. */
-      if (copylen < TYPE_LENGTH (builtin_type_long))
-	{
-	  copyarg = value_cast (builtin_type_long, copyarg);
-	  copylen = TYPE_LENGTH (builtin_type_long);
-	}
+      if (typecode == TYPE_CODE_INT   ||
+	  typecode == TYPE_CODE_BOOL  ||
+	  typecode == TYPE_CODE_CHAR  ||
+	  typecode == TYPE_CODE_RANGE ||
+	  typecode == TYPE_CODE_ENUM)
+	if (len < SPARC_INTREG_SIZE)
+	  {
+	    /* Small ints will all take up the size of one intreg on
+	       the stack.  */
+	    copyarg = value_cast (sparc_intreg_type, copyarg);
+	    copylen = SPARC_INTREG_SIZE;
+	  }
+
       write_memory (tempsp, VALUE_CONTENTS (copyarg), copylen);
       tempsp += copylen;
-      if (TYPE_CODE (VALUE_TYPE (args[x])) == TYPE_CODE_FLT && regnum < 32)
+
+      /* Corner case: Structs consisting of a single float member are floats.
+       * FIXME!  I don't know about structs containing multiple floats!
+       * Structs containing mixed floats and ints are even more weird.
+       */
+
+
+
+      /* Separate float args from all other args.  */
+      if (typecode == TYPE_CODE_FLT && SPARC_HAS_FPU)
 	{
-	  /* This gets copied into a FP register. */
-	  int nextreg = regnum + 2;
-	  char *data = VALUE_CONTENTS (args[x]);
-	  /* Floats go into the lower half of a FP register pair; quads
-	     use 2 pairs. */
-
-	  if (len == 16)
-	    nextreg += 2;
-	  else if (len == 4)
-	    regnum++;
-
-	  write_register_bytes (REGISTER_BYTE (FP0_REGNUM + regnum),
-				data,
-				len);
-	  regnum = nextreg;
+	  if (register_counter < 16)
+	    {
+	      /* This arg gets copied into a FP register. */
+	      int fpreg;
+
+	      switch (len) {
+	      case 4:	/* Single-precision (float) */
+		fpreg = FP0_REGNUM + 2 * register_counter + 1;
+		register_counter += 1;
+		break;
+	      case 8:	/* Double-precision (double) */
+		fpreg = FP0_REGNUM + 2 * register_counter;
+		register_counter += 1;
+		break;
+	      case 16:	/* Quad-precision (long double) */
+		fpreg = FP0_REGNUM + 2 * register_counter;
+		register_counter += 2;
+		break;
+	      }
+	      write_register_bytes (REGISTER_BYTE (fpreg),
+				    VALUE_CONTENTS (args[i]),
+				    len);
+	    }
 	}
+      else /* all other args go into the first six 'o' registers */
+        {
+          for (j = 0; 
+	       j < len && register_counter < 6; 
+	       j += SPARC_INTREG_SIZE)
+	    {
+	      int oreg = O0_REGNUM + register_counter;
+
+	      write_register_gen (oreg, VALUE_CONTENTS (copyarg) + j);
+	      register_counter += 1;
+	    }
+        }
     }
   return sp;
 }
 
 /* Values <= 32 bytes are returned in o0-o3 (floating-point values are
    returned in f0-f3). */
+
 void
-sparc64_extract_return_value (type, regbuf, valbuf, bitoffset)
+sp64_extract_return_value (type, regbuf, valbuf, bitoffset)
      struct type *type;
      char *regbuf;
      char *valbuf;
@@ -2130,12 +2494,12 @@ sparc64_extract_return_value (type, regbuf, valbuf, bitoffset)
 
 	  if (typecode == TYPE_CODE_STRUCT)
 	    {
-	      sparc64_extract_return_value (f->type,
-					    regbuf,
-					    valbuf,
-					    bitoffset + f->loc.bitpos);
+	      sp64_extract_return_value (f->type,
+					 regbuf,
+					 valbuf,
+					 bitoffset + f->loc.bitpos);
 	    }
-	  else if (typecode == TYPE_CODE_FLT)
+	  else if (typecode == TYPE_CODE_FLT && SPARC_HAS_FPU)
 	    {
 	      memcpy (valbuf + where, &f0[whichreg * 4] + remainder, size);
 	    }
@@ -2147,5 +2511,761 @@ sparc64_extract_return_value (type, regbuf, valbuf, bitoffset)
     }
 }
 
+extern void
+sparc64_extract_return_value (struct type *type, char *regbuf, char *valbuf)
+{
+  sp64_extract_return_value (type, regbuf, valbuf, 0);
+}
+
+extern void 
+sparclet_extract_return_value (struct type *type,
+			       char *regbuf, 
+			       char *valbuf)
+{
+  regbuf += REGISTER_RAW_SIZE (O0_REGNUM) * 8;
+  if (TYPE_LENGTH (type) < REGISTER_RAW_SIZE (O0_REGNUM))
+    regbuf += REGISTER_RAW_SIZE (O0_REGNUM) - TYPE_LENGTH (type);
+
+  memcpy ((void *) valbuf, regbuf, TYPE_LENGTH (type));
+}
+
+
+extern CORE_ADDR
+sparc32_stack_align (CORE_ADDR addr)
+{
+  return ((addr + 7) & -8);
+}
+
+extern CORE_ADDR
+sparc64_stack_align (CORE_ADDR addr)
+{
+  return ((addr + 15) & -16);
+}
+
+extern void
+sparc_print_extra_frame_info (struct frame_info *fi)
+{
+  if (fi && fi->extra_info && fi->extra_info->flat)
+    printf_filtered (" flat, pc saved at 0x%s, fp saved at 0x%s\n",
+		     paddr_nz (fi->extra_info->pc_addr), 
+		     paddr_nz (fi->extra_info->fp_addr));
+}
+
+/* MULTI_ARCH support */
+
+static char *
+sparc32_register_name (int regno)
+{
+  static char *register_names[] = 
+  { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
+    "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
+    "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
+    "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
+
+    "f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
+    "f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
+    "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+    "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
+
+    "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
+  };
+
+  if (regno < 0 ||
+      regno >= (sizeof (register_names) / sizeof (register_names[0])))
+    return NULL;
+  else
+    return register_names[regno];
+}
+
+static char *
+sparc64_register_name (int regno)
+{
+  static char *register_names[] = 
+  { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
+    "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
+    "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
+    "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
+
+    "f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
+    "f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
+    "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+    "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
+    "f32", "f34", "f36", "f38", "f40", "f42", "f44", "f46",
+    "f48", "f50", "f52", "f54", "f56", "f58", "f60", "f62",
+
+    "pc", "npc", "ccr", "fsr", "fprs", "y", "asi", "ver", 
+    "tick", "pil", "pstate", "tstate", "tba", "tl", "tt", "tpc", 
+    "tnpc", "wstate", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
+    "asr16", "asr17", "asr18", "asr19", "asr20", "asr21", "asr22", "asr23", 
+    "asr24", "asr25", "asr26", "asr27", "asr28", "asr29", "asr30", "asr31",
+    /* These are here at the end to simplify removing them if we have to.  */
+    "icc", "xcc", "fcc0", "fcc1", "fcc2", "fcc3"
+  };
+
+  if (regno < 0 ||
+      regno >= (sizeof (register_names) / sizeof (register_names[0])))
+    return NULL;
+  else
+    return register_names[regno];
+}
+
+static char *
+sparclite_register_name (int regno)
+{
+  static char *register_names[] = 
+  { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
+    "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
+    "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
+    "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
+
+    "f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
+    "f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
+    "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
+    "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
+
+    "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr",
+    "dia1", "dia2", "dda1", "dda2", "ddv1", "ddv2", "dcr", "dsr" 
+  };
+
+  if (regno < 0 ||
+      regno >= (sizeof (register_names) / sizeof (register_names[0])))
+    return NULL;
+  else
+    return register_names[regno];
+}
+
+static char *
+sparclet_register_name (int regno)
+{
+  static char *register_names[] = 
+  { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
+    "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
+    "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
+    "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
+
+    "", "", "", "", "", "", "", "", /* no floating point registers */
+    "", "", "", "", "", "", "", "",
+    "", "", "", "", "", "", "", "",
+    "", "", "", "", "", "", "", "",
+
+    "y", "psr", "wim", "tbr", "pc", "npc", "", "", /* no FPSR or CPSR */
+    "ccsr", "ccpr", "cccrcr", "ccor", "ccobr", "ccibr", "ccir", "", 
+
+    /*       ASR15                 ASR19 (don't display them) */    
+    "asr1",  "", "asr17", "asr18", "", "asr20", "asr21", "asr22"
+    /* None of the rest get displayed */
+#if 0
+    "awr0",  "awr1",  "awr2",  "awr3",  "awr4",  "awr5",  "awr6",  "awr7",  
+    "awr8",  "awr9",  "awr10", "awr11", "awr12", "awr13", "awr14", "awr15", 
+    "awr16", "awr17", "awr18", "awr19", "awr20", "awr21", "awr22", "awr23", 
+    "awr24", "awr25", "awr26", "awr27", "awr28", "awr29", "awr30", "awr31", 
+    "apsr"
+#endif /* 0 */
+  };
+
+  if (regno < 0 ||
+      regno >= (sizeof (register_names) / sizeof (register_names[0])))
+    return NULL;
+  else
+    return register_names[regno];
+}
+
+CORE_ADDR
+sparc_push_return_address (CORE_ADDR pc_unused, CORE_ADDR sp)
+{
+  if (CALL_DUMMY_LOCATION == AT_ENTRY_POINT)
+    {
+      /* The return PC of the dummy_frame is the former 'current' PC
+	 (where we were before we made the target function call).
+	 This is saved in %i7 by push_dummy_frame.
+
+	 We will save the 'call dummy location' (ie. the address
+	 to which the target function will return) in %o7.  
+	 This address will actually be the program's entry point.  
+	 There will be a special call_dummy breakpoint there.  */
+
+      write_register (O7_REGNUM, 
+		      CALL_DUMMY_ADDRESS () - 8);
+    }
+
+  return sp;
+}
+
+/* Should call_function allocate stack space for a struct return?  */
+
+static int
+sparc64_use_struct_convention (int gcc_p, struct type *type)
+{
+  return (TYPE_LENGTH (type) > 32);
+}
+
+/* Store the address of the place in which to copy the structure the
+   subroutine will return.  This is called from call_function_by_hand.
+   The ultimate mystery is, tho, what is the value "16"?
+
+   MVS: That's the offset from where the sp is now, to where the
+   subroutine is gonna expect to find the struct return address.  */
+
+static void
+sparc32_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
+{
+  char *val;
+  CORE_ADDR o7;
+
+  val = alloca (SPARC_INTREG_SIZE); 
+  store_unsigned_integer (val, SPARC_INTREG_SIZE, addr);
+  write_memory (sp + (16 * SPARC_INTREG_SIZE), val, SPARC_INTREG_SIZE); 
+
+  if (CALL_DUMMY_LOCATION == AT_ENTRY_POINT)
+    {
+      /* Now adjust the value of the link register, which was previously
+	 stored by push_return_address.  Functions that return structs are
+	 peculiar in that they return to link register + 12, rather than
+	 link register + 8.  */
+
+      o7 = read_register (O7_REGNUM);
+      write_register (O7_REGNUM, o7 - 4);
+    }
+}
+
+static void
+sparc64_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
+{
+  /* FIXME: V9 uses %o0 for this.  */
+  /* FIXME MVS: Only for small enough structs!!! */
 
+  target_write_memory (sp + (16 * SPARC_INTREG_SIZE), 
+		       (char *) &addr, SPARC_INTREG_SIZE); 
+#if 0
+  if (CALL_DUMMY_LOCATION == AT_ENTRY_POINT)
+    {
+      /* Now adjust the value of the link register, which was previously
+	 stored by push_return_address.  Functions that return structs are
+	 peculiar in that they return to link register + 12, rather than
+	 link register + 8.  */
+
+      write_register (O7_REGNUM, read_register (O7_REGNUM) - 4);
+    }
 #endif
+}
+
+/* Default target data type for register REGNO.  */
+
+static struct type *
+sparc32_register_virtual_type (int regno)
+{
+  if (regno == PC_REGNUM ||
+      regno == FP_REGNUM ||
+      regno == SP_REGNUM)
+    return builtin_type_unsigned_int;
+  if (regno < 32)
+    return builtin_type_int;
+  if (regno < 64)
+    return builtin_type_float;
+  return builtin_type_int;
+}
+
+static struct type *
+sparc64_register_virtual_type (int regno)
+{
+  if (regno == PC_REGNUM ||
+      regno == FP_REGNUM ||
+      regno == SP_REGNUM)
+    return builtin_type_unsigned_long_long;
+  if (regno < 32)
+    return builtin_type_long_long;
+  if (regno < 64)
+    return builtin_type_float;
+  if (regno < 80)
+    return builtin_type_double;
+  return builtin_type_long_long;
+}
+
+/* Number of bytes of storage in the actual machine representation for
+   register REGNO.  */
+
+static int
+sparc32_register_size (int regno)
+{
+  return 4;
+}
+
+static int
+sparc64_register_size (int regno)
+{
+  return (regno < 32 ? 8 : regno < 64 ? 4 : 8);
+}
+
+/* Index within the `registers' buffer of the first byte of the space
+   for register REGNO.  */
+
+static int
+sparc32_register_byte (int regno)
+{
+  return (regno * 4);
+}
+
+static int
+sparc64_register_byte (int regno)
+{
+  if (regno < 32)
+    return regno * 8;
+  else if (regno < 64)
+    return 32 * 8 + (regno - 32) * 4;
+  else if (regno < 80)
+    return 32 * 8 + 32 * 4 + (regno - 64) * 8;
+  else
+    return 64 * 8 + (regno - 80) * 8;
+}
+
+/* Advance PC across any function entry prologue instructions to reach
+   some "real" code.  SKIP_PROLOGUE_FRAMELESS_P advances the PC past
+   some of the prologue, but stops as soon as it knows that the
+   function has a frame.  Its result is equal to its input PC if the
+   function is frameless, unequal otherwise.  */
+
+static CORE_ADDR
+sparc_gdbarch_skip_prologue (CORE_ADDR ip)
+{
+  return examine_prologue (ip, 0, NULL, NULL);
+}
+
+/* Immediately after a function call, return the saved pc.
+   Can't go through the frames for this because on some machines
+   the new frame is not set up until the new function executes
+   some instructions.  */
+
+static CORE_ADDR
+sparc_saved_pc_after_call (struct frame_info *fi)
+{
+  return sparc_pc_adjust (read_register (RP_REGNUM));
+}
+
+/* Convert registers between 'raw' and 'virtual' formats.
+   They are the same on sparc, so there's nothing to do.  */
+
+static void
+sparc_convert_to_virtual (int regnum, struct type *type, char *from, char *to)
+{	/* do nothing (should never be called) */
+}
+
+static void
+sparc_convert_to_raw (struct type *type, int regnum, char *from, char *to)
+{	/* do nothing (should never be called) */
+}
+
+/* Init saved regs: nothing to do, just a place-holder function.  */
+
+static void
+sparc_frame_init_saved_regs (struct frame_info *fi_ignored)
+{	/* no-op */
+}
+
+/* The frame address: stored in the 'frame' field of the frame_info.  */
+
+static CORE_ADDR
+sparc_frame_address (struct frame_info *fi)
+{
+  return fi->frame;
+}
+
+/* gdbarch fix call dummy:
+   All this function does is rearrange the arguments before calling
+   sparc_fix_call_dummy (which does the real work).  */
+
+static void
+sparc_gdbarch_fix_call_dummy (char *dummy, 
+			      CORE_ADDR pc, 
+			      CORE_ADDR fun, 
+			      int nargs, 
+			      struct value **args, 
+			      struct type *type, 
+			      int gcc_p)
+{
+  if (CALL_DUMMY_LOCATION == ON_STACK)
+    sparc_fix_call_dummy (dummy, pc, fun, type, gcc_p);
+}
+
+/* Coerce float to double: a no-op.  */
+
+static int
+sparc_coerce_float_to_double (struct type *formal, struct type *actual)
+{
+  return 1;
+}
+
+/* CALL_DUMMY_ADDRESS: fetch the breakpoint address for a call dummy.  */
+
+static CORE_ADDR
+sparc_call_dummy_address (void)
+{
+  return (CALL_DUMMY_START_OFFSET) + CALL_DUMMY_BREAKPOINT_OFFSET;
+}
+
+/* Supply the Y register number to those that need it.  */
+
+int
+sparc_y_regnum (void)
+{
+  return gdbarch_tdep (current_gdbarch)->y_regnum;
+}
+
+int
+sparc_reg_struct_has_addr (int gcc_p, struct type *type)
+{
+  if (GDB_TARGET_IS_SPARC64)
+    return (TYPE_LENGTH (type) > 32);
+  else
+    return (gcc_p != 1);
+}
+
+int
+sparc_intreg_size (void)
+{
+  return SPARC_INTREG_SIZE;
+}
+
+static int
+sparc_return_value_on_stack (struct type *type)
+{
+  if (TYPE_CODE (type) == TYPE_CODE_FLT &&
+      TYPE_LENGTH (type) > 8)
+    return 1;
+  else
+    return 0;
+}
+
+/*
+ * Gdbarch "constructor" function.
+ */
+
+#define SPARC32_CALL_DUMMY_ON_STACK
+
+#define SPARC_SP_REGNUM    14
+#define SPARC_FP_REGNUM    30
+#define SPARC_FP0_REGNUM   32
+#define SPARC32_NPC_REGNUM 69
+#define SPARC32_PC_REGNUM  68
+#define SPARC32_Y_REGNUM   64
+#define SPARC64_PC_REGNUM  80
+#define SPARC64_NPC_REGNUM 81
+#define SPARC64_Y_REGNUM   85
+
+static struct gdbarch *
+sparc_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+{
+  struct gdbarch *gdbarch;
+  struct gdbarch_tdep *tdep;
+
+  static LONGEST call_dummy_32[] = 
+    { 0xbc100001, 0x9de38000, 0xbc100002, 0xbe100003,
+      0xda03a058, 0xd803a054, 0xd603a050, 0xd403a04c,
+      0xd203a048, 0x40000000, 0xd003a044, 0x01000000,
+      0x91d02001, 0x01000000
+    };
+  static LONGEST call_dummy_64[] = 
+    { 0x9de3bec0fd3fa7f7LL, 0xf93fa7eff53fa7e7LL,
+      0xf13fa7dfed3fa7d7LL, 0xe93fa7cfe53fa7c7LL,
+      0xe13fa7bfdd3fa7b7LL, 0xd93fa7afd53fa7a7LL,
+      0xd13fa79fcd3fa797LL, 0xc93fa78fc53fa787LL,
+      0xc13fa77fcc3fa777LL, 0xc83fa76fc43fa767LL,
+      0xc03fa75ffc3fa757LL, 0xf83fa74ff43fa747LL,
+      0xf03fa73f01000000LL, 0x0100000001000000LL,
+      0x0100000091580000LL, 0xd027a72b93500000LL,
+      0xd027a72791480000LL, 0xd027a72391400000LL,
+      0xd027a71fda5ba8a7LL, 0xd85ba89fd65ba897LL,
+      0xd45ba88fd25ba887LL, 0x9fc02000d05ba87fLL,
+      0x0100000091d02001LL, 0x0100000001000000LL 
+    };
+  static LONGEST call_dummy_nil[] = {0};
+
+  /* First see if there is already a gdbarch that can satisfy the request.  */
+  arches = gdbarch_list_lookup_by_info (arches, &info);
+  if (arches != NULL)
+    return arches->gdbarch;
+
+  /* None found: is the request for a sparc architecture? */
+  if (info.bfd_architecture != bfd_arch_sparc)
+    return NULL;	/* No; then it's not for us.  */
+
+  /* Yes: create a new gdbarch for the specified machine type.  */
+  tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
+  gdbarch = gdbarch_alloc (&info, tdep);
+
+  /* First set settings that are common for all sparc architectures.  */
+  set_gdbarch_believe_pcc_promotion (gdbarch, 1);
+  set_gdbarch_breakpoint_from_pc (gdbarch, memory_breakpoint_from_pc);
+  set_gdbarch_coerce_float_to_double (gdbarch, 
+				      sparc_coerce_float_to_double);
+  set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1);
+  set_gdbarch_call_dummy_p (gdbarch, 1);
+  set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 1);
+  set_gdbarch_decr_pc_after_break (gdbarch, 0);
+  set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
+  set_gdbarch_extract_struct_value_address (gdbarch, 
+					    sparc_extract_struct_value_address);
+  set_gdbarch_fix_call_dummy (gdbarch, sparc_gdbarch_fix_call_dummy);
+  set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
+  set_gdbarch_fp_regnum (gdbarch, SPARC_FP_REGNUM);
+  set_gdbarch_fp0_regnum (gdbarch, SPARC_FP0_REGNUM);
+  set_gdbarch_frame_args_address (gdbarch, sparc_frame_address);
+  set_gdbarch_frame_chain (gdbarch, sparc_frame_chain);
+  set_gdbarch_frame_init_saved_regs (gdbarch, sparc_frame_init_saved_regs);
+  set_gdbarch_frame_locals_address (gdbarch, sparc_frame_address);
+  set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
+  set_gdbarch_frame_saved_pc (gdbarch, sparc_frame_saved_pc);
+  set_gdbarch_frameless_function_invocation (gdbarch, 
+					     frameless_look_for_prologue);
+  set_gdbarch_get_saved_register (gdbarch, sparc_get_saved_register);
+  set_gdbarch_ieee_float (gdbarch, 1);
+  set_gdbarch_init_extra_frame_info (gdbarch, sparc_init_extra_frame_info);
+  set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
+  set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
+  set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
+  set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
+  set_gdbarch_max_register_raw_size (gdbarch, 8);
+  set_gdbarch_max_register_virtual_size (gdbarch, 8);
+#ifdef DO_CALL_DUMMY_ON_STACK
+  set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_on_stack);
+#else
+  set_gdbarch_pc_in_call_dummy (gdbarch, pc_in_call_dummy_at_entry_point);
+#endif
+  set_gdbarch_pop_frame (gdbarch, sparc_pop_frame);
+  set_gdbarch_push_return_address (gdbarch, sparc_push_return_address);
+  set_gdbarch_push_dummy_frame (gdbarch, sparc_push_dummy_frame);
+  set_gdbarch_read_pc (gdbarch, generic_target_read_pc);
+  set_gdbarch_register_convert_to_raw (gdbarch, sparc_convert_to_raw);
+  set_gdbarch_register_convert_to_virtual (gdbarch, 
+					   sparc_convert_to_virtual);
+  set_gdbarch_register_convertible (gdbarch, 
+				    generic_register_convertible_not);
+  set_gdbarch_reg_struct_has_addr (gdbarch, sparc_reg_struct_has_addr);
+  set_gdbarch_return_value_on_stack (gdbarch, sparc_return_value_on_stack);
+  set_gdbarch_saved_pc_after_call (gdbarch, sparc_saved_pc_after_call);
+  set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
+  set_gdbarch_skip_prologue (gdbarch, sparc_gdbarch_skip_prologue);
+  set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM);
+  set_gdbarch_use_generic_dummy_frames (gdbarch, 0);
+  set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
+
+  /*
+   * Settings that depend only on 32/64 bit word size 
+   */
+
+  switch (info.bfd_arch_info->mach)
+    {
+    case bfd_mach_sparc:
+    case bfd_mach_sparc_sparclet:
+    case bfd_mach_sparc_sparclite:
+    case bfd_mach_sparc_v8plus:
+    case bfd_mach_sparc_v8plusa:
+    case bfd_mach_sparc_sparclite_le:
+      /* 32-bit machine types: */
+
+#ifdef SPARC32_CALL_DUMMY_ON_STACK
+      set_gdbarch_call_dummy_address (gdbarch, sparc_call_dummy_address);
+      set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0x30);
+      set_gdbarch_call_dummy_length (gdbarch, 0x38);
+      set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
+      set_gdbarch_call_dummy_words (gdbarch, call_dummy_32);
+#else
+      set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
+      set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
+      set_gdbarch_call_dummy_length (gdbarch, 0);
+      set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
+      set_gdbarch_call_dummy_words (gdbarch, call_dummy_nil);
+#endif
+      set_gdbarch_call_dummy_stack_adjust (gdbarch, 68);
+      set_gdbarch_call_dummy_start_offset (gdbarch, 0);
+      set_gdbarch_frame_args_skip (gdbarch, 68);
+      set_gdbarch_function_start_offset (gdbarch, 0);
+      set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
+      set_gdbarch_npc_regnum (gdbarch, SPARC32_NPC_REGNUM);
+      set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM);
+      set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
+      set_gdbarch_push_arguments (gdbarch, sparc32_push_arguments);
+      set_gdbarch_read_fp (gdbarch, generic_target_read_fp);
+      set_gdbarch_read_sp (gdbarch, generic_target_read_sp);
+
+      set_gdbarch_register_byte (gdbarch, sparc32_register_byte);
+      set_gdbarch_register_raw_size (gdbarch, sparc32_register_size);
+      set_gdbarch_register_size (gdbarch, 4);
+      set_gdbarch_register_virtual_size (gdbarch, sparc32_register_size);
+      set_gdbarch_register_virtual_type (gdbarch, 
+					 sparc32_register_virtual_type);
+#ifdef SPARC32_CALL_DUMMY_ON_STACK
+      set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (call_dummy_32));
+#else
+      set_gdbarch_sizeof_call_dummy_words (gdbarch, 0);
+#endif
+      set_gdbarch_stack_align (gdbarch, sparc32_stack_align);
+      set_gdbarch_store_struct_return (gdbarch, sparc32_store_struct_return);
+      set_gdbarch_use_struct_convention (gdbarch, 
+					 generic_use_struct_convention);
+      set_gdbarch_write_fp (gdbarch, generic_target_write_fp);
+      set_gdbarch_write_sp (gdbarch, generic_target_write_sp);
+      tdep->y_regnum = SPARC32_Y_REGNUM;
+      tdep->fp_max_regnum = SPARC_FP0_REGNUM + 32;
+      tdep->intreg_size = 4;
+      tdep->reg_save_offset = 0x60;
+      tdep->call_dummy_call_offset = 0x24;
+      break;
+
+    case bfd_mach_sparc_v9:
+    case bfd_mach_sparc_v9a:
+      /* 64-bit machine types: */
+    default:	/* Any new machine type is likely to be 64-bit.  */
+
+#ifdef SPARC64_CALL_DUMMY_ON_STACK
+      set_gdbarch_call_dummy_address (gdbarch, sparc_call_dummy_address);
+      set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 8 * 4);
+      set_gdbarch_call_dummy_length (gdbarch, 192);
+      set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
+      set_gdbarch_call_dummy_start_offset (gdbarch, 148);
+      set_gdbarch_call_dummy_words (gdbarch, call_dummy_64);
+#else
+      set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
+      set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
+      set_gdbarch_call_dummy_length (gdbarch, 0);
+      set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
+      set_gdbarch_call_dummy_start_offset (gdbarch, 0);
+      set_gdbarch_call_dummy_words (gdbarch, call_dummy_nil);
+#endif
+      set_gdbarch_call_dummy_stack_adjust (gdbarch, 128);
+      set_gdbarch_frame_args_skip (gdbarch, 136);
+      set_gdbarch_function_start_offset (gdbarch, 0);
+      set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
+      set_gdbarch_npc_regnum (gdbarch, SPARC64_NPC_REGNUM);
+      set_gdbarch_pc_regnum (gdbarch, SPARC64_PC_REGNUM);
+      set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT);
+      set_gdbarch_push_arguments (gdbarch, sparc64_push_arguments);
+      /* NOTE different for at_entry */
+      set_gdbarch_read_fp (gdbarch, sparc64_read_fp);
+      set_gdbarch_read_sp (gdbarch, sparc64_read_sp);
+      /* Some of the registers aren't 64 bits, but it's a lot simpler just
+	 to assume they all are (since most of them are).  */
+      set_gdbarch_register_byte (gdbarch, sparc64_register_byte);
+      set_gdbarch_register_raw_size (gdbarch, sparc64_register_size);
+      set_gdbarch_register_size (gdbarch, 8);
+      set_gdbarch_register_virtual_size (gdbarch, sparc64_register_size);
+      set_gdbarch_register_virtual_type (gdbarch, 
+					 sparc64_register_virtual_type);
+#ifdef SPARC64_CALL_DUMMY_ON_STACK
+      set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (call_dummy_64));
+#else
+      set_gdbarch_sizeof_call_dummy_words (gdbarch, 0);
+#endif
+      set_gdbarch_stack_align (gdbarch, sparc64_stack_align);
+      set_gdbarch_store_struct_return (gdbarch, sparc64_store_struct_return);
+      set_gdbarch_use_struct_convention (gdbarch, 
+					 sparc64_use_struct_convention);
+      set_gdbarch_write_fp (gdbarch, sparc64_write_fp);
+      set_gdbarch_write_sp (gdbarch, sparc64_write_sp);
+      tdep->y_regnum = SPARC64_Y_REGNUM;
+      tdep->fp_max_regnum = SPARC_FP0_REGNUM + 48;
+      tdep->intreg_size = 8;
+      tdep->reg_save_offset = 0x90;
+      tdep->call_dummy_call_offset = 148 + 4 * 5;
+      break;
+    }
+
+  /* 
+   * Settings that vary per-architecture:
+   */
+
+  switch (info.bfd_arch_info->mach)
+    {
+    case bfd_mach_sparc:
+      set_gdbarch_extract_return_value (gdbarch, sparc32_extract_return_value);
+      set_gdbarch_frame_chain_valid (gdbarch, file_frame_chain_valid);
+      set_gdbarch_num_regs (gdbarch, 72);
+      set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4);
+      set_gdbarch_register_name (gdbarch, sparc32_register_name);
+      set_gdbarch_store_return_value (gdbarch, sparc_store_return_value);
+      tdep->has_fpu = 1;	/* (all but sparclet and sparclite) */
+      tdep->fp_register_bytes = 32 * 4;
+      tdep->print_insn_mach = bfd_mach_sparc;
+      break;
+    case bfd_mach_sparc_sparclet:
+      set_gdbarch_extract_return_value (gdbarch, 
+					sparclet_extract_return_value);
+      set_gdbarch_frame_chain_valid (gdbarch, file_frame_chain_valid);
+      set_gdbarch_num_regs (gdbarch, 32 + 32 + 8 + 8 + 8);
+      set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4 + 8*4 + 8*4);
+      set_gdbarch_register_name (gdbarch, sparclet_register_name);
+      set_gdbarch_store_return_value (gdbarch, sparclet_store_return_value);
+      tdep->has_fpu = 0;	/* (all but sparclet and sparclite) */
+      tdep->fp_register_bytes = 0;
+      tdep->print_insn_mach = bfd_mach_sparc_sparclet;
+      break;
+    case bfd_mach_sparc_sparclite:
+      set_gdbarch_extract_return_value (gdbarch, sparc32_extract_return_value);
+      set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid);
+      set_gdbarch_num_regs (gdbarch, 80);
+      set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4 + 8*4);
+      set_gdbarch_register_name (gdbarch, sparclite_register_name);
+      set_gdbarch_store_return_value (gdbarch, sparc_store_return_value);
+      tdep->has_fpu = 0;	/* (all but sparclet and sparclite) */
+      tdep->fp_register_bytes = 0;
+      tdep->print_insn_mach = bfd_mach_sparc_sparclite;
+      break;
+    case bfd_mach_sparc_v8plus:
+      set_gdbarch_extract_return_value (gdbarch, sparc32_extract_return_value);
+      set_gdbarch_frame_chain_valid (gdbarch, file_frame_chain_valid);
+      set_gdbarch_num_regs (gdbarch, 72);
+      set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4);
+      set_gdbarch_register_name (gdbarch, sparc32_register_name);
+      set_gdbarch_store_return_value (gdbarch, sparc_store_return_value);
+      tdep->print_insn_mach = bfd_mach_sparc;
+      tdep->fp_register_bytes = 32 * 4;
+      tdep->has_fpu = 1;	/* (all but sparclet and sparclite) */
+      break;
+    case bfd_mach_sparc_v8plusa:
+      set_gdbarch_extract_return_value (gdbarch, sparc32_extract_return_value);
+      set_gdbarch_frame_chain_valid (gdbarch, file_frame_chain_valid);
+      set_gdbarch_num_regs (gdbarch, 72);
+      set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4);
+      set_gdbarch_register_name (gdbarch, sparc32_register_name);
+      set_gdbarch_store_return_value (gdbarch, sparc_store_return_value);
+      tdep->has_fpu = 1;	/* (all but sparclet and sparclite) */
+      tdep->fp_register_bytes = 32 * 4;
+      tdep->print_insn_mach = bfd_mach_sparc;
+      break;
+    case bfd_mach_sparc_sparclite_le:
+      set_gdbarch_extract_return_value (gdbarch, sparc32_extract_return_value);
+      set_gdbarch_frame_chain_valid (gdbarch, func_frame_chain_valid);
+      set_gdbarch_num_regs (gdbarch, 80);
+      set_gdbarch_register_bytes (gdbarch, 32*4 + 32*4 + 8*4 + 8*4);
+      set_gdbarch_register_name (gdbarch, sparclite_register_name);
+      set_gdbarch_store_return_value (gdbarch, sparc_store_return_value);
+      tdep->has_fpu = 0;	/* (all but sparclet and sparclite) */
+      tdep->fp_register_bytes = 0;
+      tdep->print_insn_mach = bfd_mach_sparc_sparclite;
+      break;
+    case bfd_mach_sparc_v9:
+      set_gdbarch_extract_return_value (gdbarch, sparc64_extract_return_value);
+      set_gdbarch_frame_chain_valid (gdbarch, file_frame_chain_valid);
+      set_gdbarch_num_regs (gdbarch, 125);
+      set_gdbarch_register_bytes (gdbarch, 32*8 + 32*8 + 45*8);
+      set_gdbarch_register_name (gdbarch, sparc64_register_name);
+      set_gdbarch_store_return_value (gdbarch, sparc_store_return_value);
+      tdep->has_fpu = 1;	/* (all but sparclet and sparclite) */
+      tdep->fp_register_bytes = 64 * 4;
+      tdep->print_insn_mach = bfd_mach_sparc_v9a;
+      break;
+    case bfd_mach_sparc_v9a:
+      set_gdbarch_extract_return_value (gdbarch, sparc64_extract_return_value);
+      set_gdbarch_frame_chain_valid (gdbarch, file_frame_chain_valid);
+      set_gdbarch_num_regs (gdbarch, 125);
+      set_gdbarch_register_bytes (gdbarch, 32*8 + 32*8 + 45*8);
+      set_gdbarch_register_name (gdbarch, sparc64_register_name);
+      set_gdbarch_store_return_value (gdbarch, sparc_store_return_value);
+      tdep->has_fpu = 1;	/* (all but sparclet and sparclite) */
+      tdep->fp_register_bytes = 64 * 4;
+      tdep->print_insn_mach = bfd_mach_sparc_v9a;
+      break;
+    }
+
+  return gdbarch;
+}
+
diff --git a/gdb/sparclet-rom.c b/gdb/sparclet-rom.c
index bb11c97..6c2e770 100644
--- a/gdb/sparclet-rom.c
+++ b/gdb/sparclet-rom.c
@@ -61,7 +61,32 @@ static void sparclet_open PARAMS ((char *args, int from_tty));
 
 /* is wim part of psr?? */
 /* monitor wants lower case */
-static char *sparclet_regnames[NUM_REGS] = REGISTER_NAMES;
+static char *sparclet_regnames[] = {
+  "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", 
+  "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7", 
+  "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", 
+  "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7", 
+
+  "", "", "", "", "", "", "", "", /* no FPU regs */
+  "", "", "", "", "", "", "", "", 
+  "", "", "", "", "", "", "", "", 
+  "", "", "", "", "", "", "", "", 
+				  /* no CPSR, FPSR */
+  "y", "psr", "wim", "tbr", "pc", "npc", "", "", 
+
+  "ccsr", "ccpr", "cccrcr", "ccor", "ccobr", "ccibr", "ccir", "", 
+
+  /*       ASR15                 ASR19 (don't display them) */  
+  "asr1",  "", "asr17", "asr18", "", "asr20", "asr21", "asr22", 
+/*
+  "awr0",  "awr1",  "awr2",  "awr3",  "awr4",  "awr5",  "awr6",  "awr7",  
+  "awr8",  "awr9",  "awr10", "awr11", "awr12", "awr13", "awr14", "awr15", 
+  "awr16", "awr17", "awr18", "awr19", "awr20", "awr21", "awr22", "awr23", 
+  "awr24", "awr25", "awr26", "awr27", "awr28", "awr29", "awr30", "awr31", 
+  "apsr",
+ */
+};
+
 
 
 /* Function: sparclet_supply_register
author	Michael Snyder <msnyder@vmware.com>	2000-05-10 20:07:25 +0000
committer	Michael Snyder <msnyder@vmware.com>	2000-05-10 20:07:25 +0000
commit	5af923b0f0e349765b08f4a92adc1030ce67ff2e (patch)
tree	26cfced85a44350b34c8cb3e26d3a42263b349b9 /gdb
parent	d2f75a6f4097075a61f4c6d47dd095d22245eed7 (diff)
download	gdb-5af923b0f0e349765b08f4a92adc1030ce67ff2e.zip gdb-5af923b0f0e349765b08f4a92adc1030ce67ff2e.tar.gz gdb-5af923b0f0e349765b08f4a92adc1030ce67ff2e.tar.bz2