gdb: fix gdbarch_tdep ODR violation

I would like to be able to use non-trivial types in gdbarch_tdep types.
This is not possible at the moment (in theory), because of the one
definition rule.

To allow it, rename all gdbarch_tdep types to <arch>_gdbarch_tdep, and
make them inherit from a gdbarch_tdep base class.  The inheritance is
necessary to be able to pass pointers to all these <arch>_gdbarch_tdep
objects to gdbarch_alloc, which takes a pointer to gdbarch_tdep.

These objects are never deleted through a base class pointer, so I
didn't include a virtual destructor.  In the future, if gdbarch objects
deletable, I could imagine that the gdbarch_tdep objects could become
owned by the gdbarch objects, and then it would become useful to have a
virtual destructor (so that the gdbarch object can delete the owned
gdbarch_tdep object).  But that's not necessary right now.

It turns out that RISC-V already has a gdbarch_tdep that is
non-default-constructible, so that provides a good motivation for this
change.

Most changes are fairly straightforward, mostly needing to add some
casts all over the place.  There is however the xtensa architecture,
doing its own little weird thing to define its gdbarch_tdep.  I did my
best to adapt it, but I can't test those changes.

Change-Id: Ic001903f91ddd106bd6ca09a79dabe8df2d69f3b

1 files changed, 68 insertions, 112 deletions

diff --git a/gdb/xtensa-tdep.h b/gdb/xtensa-tdep.h
index 55a2ed4..64e4da6 100644
--- a/gdb/xtensa-tdep.h
+++ b/gdb/xtensa-tdep.h
@@ -21,6 +21,8 @@
 #define XTENSA_TDEP_H
 
 #include "arch/xtensa.h"
+#include "gdbarch.h"
+#include "xtensa-config.h"
 
 /* XTENSA_TDEP_VERSION can/should be changed along with XTENSA_CONFIG_VERSION
    whenever the "tdep" structure changes in an incompatible way.  */
@@ -155,137 +157,91 @@ struct ctype_cache
   struct type *virtual_type;
 };
 
+#ifndef XCHAL_NUM_CONTEXTS
+# define XCHAL_NUM_CONTEXTS	0
+#endif
+
+#ifndef XCHAL_HAVE_EXCEPTIONS
+# define XCHAL_HAVE_EXCEPTIONS	1
+#endif
+
 /*  Xtensa-specific target dependencies.  */
 
-struct gdbarch_tdep
+struct xtensa_gdbarch_tdep : gdbarch_tdep
 {
-  unsigned int target_flags;
+  xtensa_gdbarch_tdep (xtensa_register_t *regmap)
+    : regmap (regmap)
+  {}
+
+  unsigned int target_flags = 0;
 
   /* Spill location for TIE register files under ocd.  */
 
-  unsigned int spill_location;
-  unsigned int spill_size;
+  unsigned int spill_location = (unsigned int) -1;
+  unsigned int spill_size = 0;
 
-  char *unused;				/* Placeholder for compatibility.  */
-  call_abi_t call_abi;			/* Calling convention.  */
+  char *unused = nullptr;		/* Placeholder for compatibility.  */
+
+  /* Calling convention.  */
+  call_abi_t call_abi = (XSHAL_ABI == XTHAL_ABI_CALL0
+			 ? CallAbiCall0Only : CallAbiDefault);
 
   /* CPU configuration.  */
 
-  unsigned int debug_interrupt_level;
+  unsigned int debug_interrupt_level = XCHAL_DEBUGLEVEL;
 
-  unsigned int icache_line_bytes;
-  unsigned int dcache_line_bytes;
-  unsigned int dcache_writeback;
+  unsigned int icache_line_bytes = XCHAL_ICACHE_LINESIZE;
+  unsigned int dcache_line_bytes = XCHAL_DCACHE_LINESIZE;
+  unsigned int dcache_writeback = XCHAL_DCACHE_IS_WRITEBACK;
 
-  unsigned int isa_use_windowed_registers;
-  unsigned int isa_use_density_instructions;
-  unsigned int isa_use_exceptions;
-  unsigned int isa_use_ext_l32r;
-  unsigned int isa_max_insn_size;	/* Maximum instruction length.  */
-  unsigned int debug_num_ibreaks;	/* Number of IBREAKs.  */
-  unsigned int debug_num_dbreaks;
+  unsigned int isa_use_windowed_registers = XSHAL_ABI != XTHAL_ABI_CALL0;
+  unsigned int isa_use_density_instructions = XCHAL_HAVE_DENSITY;
+  unsigned int isa_use_exceptions = XCHAL_HAVE_EXCEPTIONS;
+  unsigned int isa_use_ext_l32r = XSHAL_USE_ABSOLUTE_LITERALS;
+  unsigned int isa_max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE;	/* Maximum instruction length.  */
+  unsigned int debug_num_ibreaks = XCHAL_NUM_IBREAK;	/* Number of IBREAKs.  */
+  unsigned int debug_num_dbreaks = XCHAL_NUM_DBREAK;
 
   /* Register map.  */
 
-  xtensa_register_t* regmap;
-
-  unsigned int num_regs;	/* Number of registers in register map.  */
-  unsigned int num_nopriv_regs;	/* Number of non-privileged registers.  */
-  unsigned int num_pseudo_regs;	/* Number of pseudo registers.  */
-  unsigned int num_aregs;	/* Size of register file.  */
-  unsigned int num_contexts;
-
-  int ar_base;			/* Register number for AR0.  */
-  int a0_base;			/* Register number for A0 (pseudo).  */
-  int wb_regnum;		/* Register number for WB.  */
-  int ws_regnum;		/* Register number for WS.  */
-  int pc_regnum;		/* Register number for PC.  */
-  int ps_regnum;		/* Register number for PS.  */
-  int lbeg_regnum;		/* Register numbers for count regs.  */
-  int lend_regnum;
-  int lcount_regnum;
-  int sar_regnum;		/* Register number of SAR.  */
-  int litbase_regnum;		/* Register number of LITBASE.  */
-  int threadptr_regnum;		/* Register number of THREADPTR.  */
-
-  int interrupt_regnum;		/* Register number for interrupt.  */
-  int interrupt2_regnum;	/* Register number for interrupt2.  */
-  int cpenable_regnum;		/* Register number for cpenable.  */
-  int debugcause_regnum;	/* Register number for debugcause.  */
-  int exccause_regnum;		/* Register number for exccause.  */
-  int excvaddr_regnum;		/* Register number for excvaddr.  */
-
-  int max_register_raw_size;
-  int max_register_virtual_size;
-  unsigned long *fp_layout;	/* Layout of custom/TIE regs in 'FP' area.  */
-  unsigned int fp_layout_bytes;	/* Size of layout information (in bytes).  */
-  unsigned long *gregmap;
+  xtensa_register_t *regmap;
+
+  unsigned int num_regs = 0;		/* Number of registers in register map.  */
+  unsigned int num_nopriv_regs = 0;	/* Number of non-privileged registers.  */
+  unsigned int num_pseudo_regs = 0;	/* Number of pseudo registers.  */
+  unsigned int num_aregs = XCHAL_NUM_AREGS;		/* Size of register file.  */
+  unsigned int num_contexts = XCHAL_NUM_CONTEXTS;
+
+  int ar_base = -1;		/* Register number for AR0.  */
+  int a0_base = -1;		/* Register number for A0 (pseudo).  */
+  int wb_regnum = -1;		/* Register number for WB.  */
+  int ws_regnum = -1;		/* Register number for WS.  */
+  int pc_regnum = -1;		/* Register number for PC.  */
+  int ps_regnum = -1;		/* Register number for PS.  */
+  int lbeg_regnum = -1;		/* Register numbers for count regs.  */
+  int lend_regnum = -1;
+  int lcount_regnum = -1;
+  int sar_regnum = -1;		/* Register number of SAR.  */
+  int litbase_regnum = -1;	/* Register number of LITBASE.  */
+  int threadptr_regnum = -1;	/* Register number of THREADPTR.  */
+
+  int interrupt_regnum = -1;	/* Register number for interrupt.  */
+  int interrupt2_regnum = -1;	/* Register number for interrupt2.  */
+  int cpenable_regnum = -1;	/* Register number for cpenable.  */
+  int debugcause_regnum = -1;	/* Register number for debugcause.  */
+  int exccause_regnum = -1;	/* Register number for exccause.  */
+  int excvaddr_regnum = -1;	/* Register number for excvaddr.  */
+
+  int max_register_raw_size = 0;
+  int max_register_virtual_size = 0;
+  unsigned long *fp_layout = nullptr;	/* Layout of custom/TIE regs in 'FP' area.  */
+  unsigned int fp_layout_bytes = 0;	/* Size of layout information (in bytes).  */
+  unsigned long *gregmap = nullptr;
 
   /* Cached register types.  */
-  struct ctype_cache *type_entries;
+  struct ctype_cache *type_entries = nullptr;
 };
 
-/* Macro to instantiate a gdbarch_tdep structure.  */
-
-#define XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spillsz)			\
-  {									\
-    0,				/* target_flags */			\
-    (unsigned) -1,		/* spill_location */	\
-    (spillsz),			/* spill_size */			\
-    0,				/* unused */				\
-    (XSHAL_ABI == XTHAL_ABI_CALL0					\
-     ? CallAbiCall0Only							\
-     : CallAbiDefault),		/* call_abi */				\
-    XCHAL_DEBUGLEVEL,		/* debug_interrupt_level */		\
-    XCHAL_ICACHE_LINESIZE,	/* icache_line_bytes */			\
-    XCHAL_DCACHE_LINESIZE,	/* dcache_line_bytes */			\
-    XCHAL_DCACHE_IS_WRITEBACK,  /* dcache_writeback */			\
-    (XSHAL_ABI != XTHAL_ABI_CALL0),   /* isa_use_windowed_registers */	\
-    XCHAL_HAVE_DENSITY,		 /* isa_use_density_instructions */	\
-    XCHAL_HAVE_EXCEPTIONS,	 /* isa_use_exceptions */		\
-    XSHAL_USE_ABSOLUTE_LITERALS, /* isa_use_ext_l32r */			\
-    XCHAL_MAX_INSTRUCTION_SIZE,  /* isa_max_insn_size */		\
-    XCHAL_NUM_IBREAK,		 /* debug_num_ibreaks */		\
-    XCHAL_NUM_DBREAK,		 /* debug_num_dbreaks */		\
-    rmap,			 /* regmap */				\
-    0,				 /* num_regs */				\
-    0,				 /* num_nopriv_regs */			\
-    0,				 /* num_pseudo_regs */			\
-    XCHAL_NUM_AREGS,		 /* num_aregs */			\
-    XCHAL_NUM_CONTEXTS,		 /* num_contexts */			\
-    -1,				 /* ar_base */				\
-    -1,				 /* a0_base */				\
-    -1,				 /* wb_regnum */			\
-    -1,				 /* ws_regnum */			\
-    -1,				 /* pc_regnum */			\
-    -1,				 /* ps_regnum */			\
-    -1,				 /* lbeg_regnum */			\
-    -1,				 /* lend_regnum */			\
-    -1,				 /* lcount_regnum */			\
-    -1,				 /* sar_regnum */			\
-    -1,				 /* litbase_regnum */			\
-    -1,				 /* interrupt_regnum */			\
-    -1,				 /* interrupt2_regnum */		\
-    -1,				 /* cpenable_regnum */			\
-    -1,				 /* debugcause_regnum */		\
-    -1,				 /* exccause_regnum */			\
-    -1,				 /* excvaddr_regnum */			\
-    0,				 /* max_register_raw_size */		\
-    0,				 /* max_register_virtual_size */	\
-    0,				 /* fp_layout */			\
-    0,				 /* fp_layout_bytes */			\
-    0,				 /* gregmap */				\
-  }
-#define XTENSA_CONFIG_INSTANTIATE(rmap,spill_size)	\
-	struct gdbarch_tdep xtensa_tdep = \
-	  XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spill_size);
-
-#ifndef XCHAL_NUM_CONTEXTS
-#define XCHAL_NUM_CONTEXTS	0
-#endif
-#ifndef XCHAL_HAVE_EXCEPTIONS
-#define XCHAL_HAVE_EXCEPTIONS	1
-#endif
 #define WB_SHIFT	  2
 
 /* We assign fixed numbers to the registers of the "current" window