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authorSimon Marchi <simon.marchi@ericsson.com>2018-05-30 14:54:37 -0400
committerSimon Marchi <simon.marchi@ericsson.com>2018-05-30 14:54:37 -0400
commit10eaee5f56611ce5f92ccd305849c0cc6addd130 (patch)
treed7ddbdf42f173b202ee806251a9053db8f2c40d8 /gdb/xtensa-tdep.c
parent0b8835861cde41744a08f215b48fccd135815b63 (diff)
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Remove regcache_raw_write
Remove regcache_raw_write, update all callers to use regcache::raw_write instead. gdb/ChangeLog: * regcache.h (regcache_raw_write): Remove, update callers to use regcache::raw_write instead. * regcache.c (regcache_raw_write): Remove.
Diffstat (limited to 'gdb/xtensa-tdep.c')
-rw-r--r--gdb/xtensa-tdep.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/gdb/xtensa-tdep.c b/gdb/xtensa-tdep.c
index 32533e8..c23d777 100644
--- a/gdb/xtensa-tdep.c
+++ b/gdb/xtensa-tdep.c
@@ -661,7 +661,7 @@ xtensa_pseudo_register_write (struct gdbarch *gdbarch,
/* We can always write 'core' registers.
Note: We might have converted Ax->ARy. */
if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
- regcache_raw_write (regcache, regnum, buffer);
+ regcache->raw_write (regnum, buffer);
/* We have to find out how to deal with priveleged registers.
Let's treat them as pseudo-registers, but we cannot read/write them. */
@@ -718,7 +718,7 @@ xtensa_pseudo_register_write (struct gdbarch *gdbarch,
}
/* Assume that we can write the register. */
- regcache_raw_write (regcache, regnum, buffer);
+ regcache->raw_write (regnum, buffer);
}
else
internal_error (__FILE__, __LINE__,
@@ -1648,7 +1648,7 @@ xtensa_store_return_value (struct type *type,
if (len < 4)
regcache_raw_write_part (regcache, areg, offset, len, valbuf);
else
- regcache_raw_write (regcache, areg, valbuf);
+ regcache->raw_write (areg, valbuf);
}
}