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authorPierre Muller <muller@sourceware.org>2009-02-13 22:10:25 +0000
committerPierre Muller <muller@sourceware.org>2009-02-13 22:10:25 +0000
commit2ff5e6054c295e987f498887943ab1b03ae8f140 (patch)
tree8e790ef619445df315416e12b72559435be02f7d /gdb/xtensa-tdep.c
parentf488e4b0e99b9f8871013aa719ea4ff477a4f330 (diff)
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2009-02-13 Pierre Muller <muller@ics.u-strasbg.fr>
* xtensa-tdep.c (call0_analyze_prologue): Delete BSZ macro. Replace BSZ macro uses by XTENSA_ISA_BSZ macro.
Diffstat (limited to 'gdb/xtensa-tdep.c')
-rw-r--r--gdb/xtensa-tdep.c7
1 files changed, 3 insertions, 4 deletions
diff --git a/gdb/xtensa-tdep.c b/gdb/xtensa-tdep.c
index f219661..0ca54e4 100644
--- a/gdb/xtensa-tdep.c
+++ b/gdb/xtensa-tdep.c
@@ -2092,8 +2092,7 @@ call0_analyze_prologue (CORE_ADDR start, CORE_ADDR pc, CORE_ADDR litbase,
CORE_ADDR ia; /* Current insn address in prologue. */
CORE_ADDR ba = 0; /* Current address at base of insn buffer. */
CORE_ADDR bt; /* Current address at top+1 of insn buffer. */
- #define BSZ 32 /* Instruction buffer size. */
- char ibuf[BSZ]; /* Instruction buffer for decoding prologue. */
+ char ibuf[XTENSA_ISA_BSZ];/* Instruction buffer for decoding prologue. */
xtensa_isa isa; /* libisa ISA handle. */
xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */
xtensa_format ifmt; /* libisa instruction format. */
@@ -2153,7 +2152,7 @@ call0_analyze_prologue (CORE_ADDR start, CORE_ADDR pc, CORE_ADDR litbase,
if (!xtensa_default_isa)
xtensa_default_isa = xtensa_isa_init (0, 0);
isa = xtensa_default_isa;
- gdb_assert (BSZ >= xtensa_isa_maxlength (isa));
+ gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
ins = xtensa_insnbuf_alloc (isa);
slot = xtensa_insnbuf_alloc (isa);
@@ -2166,7 +2165,7 @@ call0_analyze_prologue (CORE_ADDR start, CORE_ADDR pc, CORE_ADDR litbase,
if (ia + xtensa_isa_maxlength (isa) > bt)
{
ba = ia;
- bt = (ba + BSZ) < body_pc ? ba + BSZ : body_pc;
+ bt = (ba + XTENSA_ISA_BSZ) < body_pc ? ba + XTENSA_ISA_BSZ : body_pc;
read_memory (ba, ibuf, bt - ba);
}