gdb/

	* rs6000-tdep.c (IS_EFP_PSEUDOREG): Use correct constant for
	the EFP register set size.
	(efpr_pseudo_register_read): Use regcache_raw_read_part to read
	data from the VMX register.
	(efpr_pseudo_register_write): Use regcache_raw_write_part to read
	and write data from/to the VMX register.

gdb/testsuite/
	* gdb.arch/vsx-regs.exp: Add "vector_register1_vr" and
	"vector_register2_vr" test strings.  Test the extended floating
	point registers (F32~F63).
	* lib/gdb.exp (skip_vsx_tests): Update compile flags for the
	IBM XL C compiler.  Make the test program use a register provided
	by the compiler for the lxvd2x instruction.

1 files changed, 37 insertions, 0 deletions

diff --git a/gdb/testsuite/gdb.arch/vsx-regs.exp b/gdb/testsuite/gdb.arch/vsx-regs.exp
index d42b7f3..959f90a 100644
--- a/gdb/testsuite/gdb.arch/vsx-regs.exp
+++ b/gdb/testsuite/gdb.arch/vsx-regs.exp
@@ -66,8 +66,12 @@ if ![runto_main] then {
 
 set vector_register1 ".uint128 = 0x3ff4cccccccccccc0000000000000000, v2_double = .0x1, 0x0., v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.."
 
+set vector_register1_vr ".uint128 = 0x3ff4cccccccccccc0000000100000001, v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x1, 0x1., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
+
 set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x1, 0x1., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
 
+set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.."
+
 set vector_register3 ".uint128 = 0x00000001000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
 
 set vector_register3_vr ".uint128 = 0x00000001000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.."
@@ -123,6 +127,11 @@ for {set i 0} {$i < 32} {incr i 1} {
     gdb_test "info reg vr$i" "vr$i.*$vector_register3_vr" "info reg vr$i"
 }
 
+# Create a core file.  We create the core file before the F32~F63/VR0~VR31 test
+# below because then we'll have more interesting register values to verify
+# later when loading the core file (i.e., different register values for different
+# vector register banks).
+
 set escapedfilename [string_to_regexp ${objdir}/${subdir}/vsx-core.test]
 
 set core_supported 0
@@ -142,6 +151,34 @@ gdb_test_multiple "gcore ${objdir}/${subdir}/vsx-core.test" \
   }
 }
 
+# Now run the F32~F63/VR0~VR31 tests.
+
+# 1: Set F32~F63 registers and check if it reflects on VR0~VR31.
+for {set i 32} {$i < 64} {incr i 1} {
+    gdb_test_no_output "set \$f$i = 1\.3"
+}
+
+for {set i 0} {$i < 32} {incr i 1} {
+    gdb_test "info reg vr$i" "vr$i.*$vector_register1_vr" "info reg vr$i (doubleword 0)"
+}
+
+# 2: Set VR0~VR31 registers and check if it reflects on F32~F63.
+for {set i 0} {$i < 32} {incr i 1} {
+        for {set j 0} {$j < 4} {incr j 1} {
+           gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 0xdeadbeef"
+        }
+}
+
+for {set i 32} {$i < 64} {incr i 1} {
+    gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i"
+}
+
+for {set i 0} {$i < 32} {incr i 1} {
+    gdb_test "info reg vr$i" "vr$i.*$vector_register2_vr" "info reg vr$i (doubleword 1)"
+}
+
+# Test reading the core file.
+
 if {!$core_supported} {
   return -1
 }