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| author | Richard Sandiford <richard.sandiford@arm.com> | 2016-06-18 11:13:28 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2016-08-23 09:41:04 +0100 |
| commit | 32054386cb652b0ca5ac31390c9de5b1784c133e (patch) | |
| tree | 58740ac6c18883c71a57198cae74a26c27c27e04 /gdb/syscalls/arm-linux.py | |
| parent | 936b52907bc22f1f0c4c4bf7865d6f70ceb25eb2 (diff) | |
| download | gdb-32054386cb652b0ca5ac31390c9de5b1784c133e.zip gdb-32054386cb652b0ca5ac31390c9de5b1784c133e.tar.gz gdb-32054386cb652b0ca5ac31390c9de5b1784c133e.tar.bz2 | |
[AArch64][SVE 30/32] Add SVE instruction classes
The main purpose of the SVE aarch64_insn_classes is to describe how
an index into an aarch64_opnd_qualifier_seq_t is represented in the
instruction encoding. Other instructions usually use flags for this
information, but (a) we're running out of those and (b) the iclass
would otherwise be unused for SVE.
include/opcode/
* aarch64.h (sve_cpy, sve_index, sve_limm, sve_misc, sve_movprfx)
(sve_pred_zm, sve_shift_pred, sve_shift_unpred, sve_size_bhs)
(sve_size_bhsd, sve_size_hsd, sve_size_sd): New aarch64_insn_classes.
opcodes/
* aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
(FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries.
* aarch64-asm.c (aarch64_get_variant): New function.
(aarch64_encode_variant_using_iclass): Likewise.
(aarch64_opcode_encode): Call it.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
(aarch64_opcode_decode): Call it.
Change-Id: Ia562434a84b519aecd21b4cd7d3f5e2dfb9af67d
Diffstat (limited to 'gdb/syscalls/arm-linux.py')
0 files changed, 0 insertions, 0 deletions