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| author | Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com> | 2003-10-10 07:13:11 +0000 |
|---|---|---|
| committer | Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com> | 2003-10-10 07:13:11 +0000 |
| commit | 85a453d5416fd260a4516796d7e230f7b20577de (patch) | |
| tree | 055db7a62b4cc61a59dd95e60ddf8cb20ba50001 /gdb/sh-stub.c | |
| parent | 172c2a4375234c73f74113a88adfea6dc86e0a62 (diff) | |
| download | gdb-85a453d5416fd260a4516796d7e230f7b20577de.zip gdb-85a453d5416fd260a4516796d7e230f7b20577de.tar.gz gdb-85a453d5416fd260a4516796d7e230f7b20577de.tar.bz2 | |
2003-10-10 Kei Sakamoto <sakamoto.kei@renesas.com>
* NEWS: Replace "Hitachi" and "Mitsubishi" with "Renesas".
* README: Ditto.
* d10v-tdep.c: Ditto.
* h8300-tdep.c: Ditto.
* remote-e7000.c: Ditto.
* remote-hms.c: Ditto.
* ser-e7kpc.c: Ditto.
* sh-stub.c: Ditto.
* sh-tdep.c: Ditto.
* sh-tdep.h: Ditto.
* sh3-rom.c: Ditto.
* sh64-tdep.c: Ditto.
* top.c: Ditto.
* wince.c: Ditto.
* config/d10v/d10v.mt: Ditto.
* config/sh/embed.mt: Ditto.
* config/sh/linux.mt: Ditto.
* config/sh/tm-linux.h: Ditto.
* config/sh/tm-sh.h: Ditto.
* config/sh/wince.mt: Ditto.
Diffstat (limited to 'gdb/sh-stub.c')
| -rw-r--r-- | gdb/sh-stub.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/gdb/sh-stub.c b/gdb/sh-stub.c index 73357b4..bdd9e50 100644 --- a/gdb/sh-stub.c +++ b/gdb/sh-stub.c @@ -1,4 +1,4 @@ -/* sh-stub.c -- debugging stub for the Hitachi-SH. +/* sh-stub.c -- debugging stub for the Renesas-SH. NOTE!! This code has to be compiled with optimization, otherwise the function inlining which generates the exception handlers won't work. @@ -147,7 +147,7 @@ #include <string.h> #include <setjmp.h> -/* Hitachi SH architecture instruction encoding masks */ +/* Renesas SH architecture instruction encoding masks */ #define COND_BR_MASK 0xff00 #define UCOND_DBR_MASK 0xe000 @@ -158,7 +158,7 @@ #define UCOND_DISP 0x0fff #define UCOND_REG 0x0f00 -/* Hitachi SH instruction opcodes */ +/* Renesas SH instruction opcodes */ #define BF_INSTR 0x8b00 #define BT_INSTR 0x8900 @@ -171,7 +171,7 @@ #define TRAPA_INSTR 0xc300 #define SSTEP_INSTR 0xc3ff -/* Hitachi SH processor register masks */ +/* Renesas SH processor register masks */ #define T_BIT_MASK 0x0001 @@ -824,7 +824,7 @@ breakpoint (void) /* Note: - The Hitachi SH family uses two exception architectures: + The Renesas SH family uses two exception architectures: SH1 & SH2: |