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| author | Maciej W. Rozycki <macro@codesourcery.com> | 2014-03-18 19:39:41 +0000 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@codesourcery.com> | 2014-03-18 19:48:14 +0000 |
| commit | dea80df0999ae0bad56e79af2a88a30be38bb8e4 (patch) | |
| tree | 797d4ceb2ac94f8a3a01e3d0ee5b4a30441e8e6c /gdb/rs6000-tdep.c | |
| parent | 0c7e1a4602a41a1caf637823f67948be31d27732 (diff) | |
| download | gdb-dea80df0999ae0bad56e79af2a88a30be38bb8e4.zip gdb-dea80df0999ae0bad56e79af2a88a30be38bb8e4.tar.gz gdb-dea80df0999ae0bad56e79af2a88a30be38bb8e4.tar.bz2 | |
Power: Correct little-endian e500v2 GPR frame offsets
This change corrects GPR frame offset calculation for the e500v2
processor. On this target, featuring the SPE APU, GPRs are 64-bit and
are held in stack frames whole with the use of `evstdd' and `evldd'
instructions. Their integer 32-bit part occupies the low-order word and
therefore its offset varies between the two endiannesses possible.
* rs6000-tdep.c (rs6000_frame_cache): Correct little-endian GPR
offset into SPE pseudo registers.
Diffstat (limited to 'gdb/rs6000-tdep.c')
| -rw-r--r-- | gdb/rs6000-tdep.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c index bec06c7..dbe3aa2 100644 --- a/gdb/rs6000-tdep.c +++ b/gdb/rs6000-tdep.c @@ -3257,12 +3257,14 @@ rs6000_frame_cache (struct frame_info *this_frame, void **this_cache) { int i; CORE_ADDR ev_addr = cache->base + fdata.ev_offset; + CORE_ADDR off = (byte_order == BFD_ENDIAN_BIG ? 4 : 0); + for (i = fdata.saved_ev; i < ppc_num_gprs; i++) { cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr; - cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4; + cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + off; ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum); - } + } } } |