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authorAndrew Burgess <andrew.burgess@embecosm.com>2020-11-11 11:55:08 +0000
committerAndrew Burgess <andrew.burgess@embecosm.com>2020-11-11 11:55:08 +0000
commit550820e16d0a1f44ee63086b1a2d931e04839ffa (patch)
tree8cab9812e2a3868d92c1b5cce445ee0dc8299344 /gdb/riscv-tdep.h
parent81fdd7acec68476bc23dd1ed4b2c6288aebe4343 (diff)
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gdb/riscv: add ability to decode dwarf CSR numbers
Extends riscv_dwarf_reg_to_regnum to add the ability to convert the DWARF register numbers for CSRs into GDB's internal numbers. gdb/ChangeLog: * riscv-tdep.c (riscv_dwarf_reg_to_regnum): Decode DWARF CSR numbers. * riscv-tdep.h (RISCV_DWARF_FIRST_CSR, RISCV_DWARF_LAST_CSR): New enum values.
Diffstat (limited to 'gdb/riscv-tdep.h')
-rw-r--r--gdb/riscv-tdep.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h
index 0ff555b..5bd3314 100644
--- a/gdb/riscv-tdep.h
+++ b/gdb/riscv-tdep.h
@@ -63,6 +63,8 @@ enum
RISCV_DWARF_REGNUM_X31 = 31,
RISCV_DWARF_REGNUM_F0 = 32,
RISCV_DWARF_REGNUM_F31 = 63,
+ RISCV_DWARF_FIRST_CSR = 4096,
+ RISCV_DWARF_LAST_CSR = 8191,
};
/* RISC-V specific per-architecture information. */