gdb: Initial baremetal riscv support

This commit introduces basic support for baremetal RiscV as a GDB
target.  This target is currently only tested against the RiscV software
simulator, which is not included as part of this commit.  The target has
been tested against the following RiscV variants: rv32im, rv32imc,
rv32imf, rv32imfc, rv64im, rv64imc, rv64imfd, rv64imfdc.

Across these variants we pass on average 34858 tests, and fail 272
tests, which is ~0.8%.

The RiscV has a feature of its ABI where structures with a single
floating point field, a single complex float field, or one float and
one integer field are treated differently for argument passing.  The
new test gdb.base/infcall-nested-structs.exp is added to cover this
feature.  As passing these structures should work on all targets then
I've made the test as a generic one, even though, for most targets,
there's probably nothing special about any of these cases.

gdb/ChangeLog:

	* Makefile.in (ALL_TARGET_OBS): Add riscv-tdep.o
	(HFILES_NO_SRCDIR): Add riscv-tdep.h.
	(ALLDEPFILES): Add riscv-tdep.c
	* configure.tgt: Add riscv support.
	* riscv-tdep.c: New file.
	* riscv-tdep.h: New file.
	* NEWS: Mention new target.
	* MAINTAINERS: Add entry for riscv.

gdb/testsuite/ChangeLog:

	* gdb.base/infcall-nested-structs.exp: New file.
	* gdb.base/infcall-nested-structs.c: New file.
	* gdb.base/float.exp: Add riscv support.

1 files changed, 84 insertions, 0 deletions

diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h
new file mode 100644
index 0000000..3c033dc
--- /dev/null
+++ b/gdb/riscv-tdep.h
@@ -0,0 +1,84 @@
+/* Target-dependent header for the RISC-V architecture, for GDB, the GNU Debugger.
+
+   Copyright (C) 2018 Free Software Foundation, Inc.
+
+   Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
+   and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin
+   and by Todd Snyder <todd@bluespec.com>
+   and by Mike Frysinger <vapier@gentoo.org>.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#ifndef RISCV_TDEP_H
+#define RISCV_TDEP_H
+
+/* RiscV register numbers.  */
+enum
+{
+  RISCV_ZERO_REGNUM = 0,	/* Read-only register, always 0.  */
+  RISCV_RA_REGNUM = 1,		/* Return Address.  */
+  RISCV_SP_REGNUM = 2,		/* Stack Pointer.  */
+  RISCV_GP_REGNUM = 3,		/* Global Pointer.  */
+  RISCV_TP_REGNUM = 4,		/* Thread Pointer.  */
+  RISCV_FP_REGNUM = 8,		/* Frame Pointer.  */
+  RISCV_A0_REGNUM = 10,		/* First argument.  */
+  RISCV_A1_REGNUM = 11,		/* Second argument.  */
+  RISCV_PC_REGNUM = 32,		/* Program Counter.  */
+
+  RISCV_FIRST_FP_REGNUM = 33,	/* First Floating Point Register */
+  RISCV_FA0_REGNUM = 43,
+  RISCV_FA1_REGNUM = RISCV_FA0_REGNUM + 1,
+  RISCV_LAST_FP_REGNUM = 64,	/* Last Floating Point Register */
+
+  RISCV_FIRST_CSR_REGNUM = 65,  /* First CSR */
+#define DECLARE_CSR(name, num) RISCV_ ## num ## _REGNUM = RISCV_LAST_FP_REGNUM + 1 + num,
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR
+  RISCV_LAST_CSR_REGNUM = 4160,
+  RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10,
+
+  RISCV_PRIV_REGNUM = 4161,
+
+  RISCV_LAST_REGNUM = RISCV_PRIV_REGNUM
+};
+
+/* RISC-V specific per-architecture information.  */
+struct gdbarch_tdep
+{
+  union
+  {
+    /* Provide access to the whole ABI in one value.  */
+    unsigned value;
+
+    struct
+    {
+      /* Encode the base machine length following the same rules as in the
+	 MISA register.  */
+      unsigned base_len : 2;
+
+      /* Encode which floating point ABI is in use following the same rules
+	 as the ELF e_flags field.  */
+      unsigned float_abi : 2;
+    } fields;
+  } abi;
+
+  /* Only the least significant 26 bits are (possibly) valid, and indicate
+     features that are supported on the target.  These could be cached from
+     the target, or read from the executable when available.  */
+  unsigned core_features;
+};
+
+#endif /* RISCV_TDEP_H */