gdb/riscv: Provide non-DWARF stack unwinder

Collects information during the prologue scan and uses this to unwind
registers when no DWARF information is available.

This patch has been tested by disabling the DWARF stack unwinders, and
running the complete GDB testsuite against a range of RISC-V targets.
The results are comparable to running with the DWARF unwinders in
place.

gdb/ChangeLog:

	* riscv-tdep.c: Add 'prologue-value.h' include.
	(struct riscv_unwind_cache): New struct.
	(riscv_debug_unwinder): New global.
	(riscv_scan_prologue): Update arguments, capture register details
	from prologue scan.
	(riscv_skip_prologue): Reformat arguments line, move end of
	prologue calculation into riscv_scan_prologue.
	(riscv_frame_cache): Update return type, create
	riscv_unwind_cache, scan the prologue, and fill in remaining cache
	details.
	(riscv_frame_this_id): Use frame id computed in riscv_frame_cache.
	(riscv_frame_prev_register): Use the trad_frame within the
	riscv_unwind_cache.
	(_initialize_riscv_tdep): Add 'set/show debug riscv unwinder'
	flag.

1 files changed, 2 insertions, 0 deletions

diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h
index 8358d4e..8a2454e 100644
--- a/gdb/riscv-tdep.h
+++ b/gdb/riscv-tdep.h
@@ -34,6 +34,8 @@ enum
   RISCV_A1_REGNUM = 11,		/* Second argument.  */
   RISCV_PC_REGNUM = 32,		/* Program Counter.  */
 
+  RISCV_NUM_INTEGER_REGS = 32,
+
   RISCV_FIRST_FP_REGNUM = 33,	/* First Floating Point Register */
   RISCV_FA0_REGNUM = 43,
   RISCV_FA1_REGNUM = RISCV_FA0_REGNUM + 1,