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authorAndrew Burgess <andrew.burgess@embecosm.com>2020-12-02 15:10:06 +0000
committerAndrew Burgess <andrew.burgess@embecosm.com>2021-01-18 14:14:11 +0000
commit6a9ad81c449922e8c0d3228c18422f68136eef17 (patch)
tree7d9dfb01516aed307b3f1531b8a00dc12296ff0c /gdb/riscv-tdep.c
parent326adec374dd43086dbf9bb2b8f18d547389e678 (diff)
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gdb/riscv: use a single regset supply function for riscv fbsd & linux
The RISC-V x0 register is hard-coded to zero. As such neither Linux or FreeBSD supply the value of the register x0 in their core dump files. For FreeBSD we take care of this by manually supplying the value of x0 in riscv_fbsd_supply_gregset, however we don't do this for Linux. As a result after loading a core file on Linux we see this behaviour: (gdb) p $x0 $1 = <unavailable> In this commit I make riscv_fbsd_supply_gregset a common function that can be shared between RISC-V for FreeBSD and Linux, this resolves the above issue. There is a similar problem for the two registers `fflags` and `frm`. These two floating point related CSRs are a little weird. They are separate CSRs in the RISC-V specification, but are actually sub-fields of the `fcsr` CSR. As a result neither Linux or FreeBSD supply the `fflags` or `frm` registers as separate fields in their core dumps, and so, after restoring a core dump these register are similarly unavailable. In this commit I supply `fflags` and `frm` by first asking for the value of `fcsr`, extracting the two fields, and using these to supply the values for `fflags` and `frm`. gdb/ChangeLog: * riscv-fbsd-tdep.c (riscv_fbsd_supply_gregset): Delete. (riscv_fbsd_gregset): Use riscv_supply_regset. (riscv_fbsd_fpregset): Likewise. * riscv-linux-tdep.c (riscv_linux_gregset): Likewise. (riscv_linux_fregset): Likewise. * riscv-tdep.c (riscv_supply_regset): Define new function. * riscv-tdep.h (riscv_supply_regset): Declare new function.
Diffstat (limited to 'gdb/riscv-tdep.c')
-rw-r--r--gdb/riscv-tdep.c50
1 files changed, 50 insertions, 0 deletions
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index c0e84e5..b16e7d7 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -3786,6 +3786,56 @@ riscv_init_reggroups ()
csr_reggroup = reggroup_new ("csr", USER_REGGROUP);
}
+/* See riscv-tdep.h. */
+
+void
+riscv_supply_regset (const struct regset *regset,
+ struct regcache *regcache, int regnum,
+ const void *regs, size_t len)
+{
+ regcache->supply_regset (regset, regnum, regs, len);
+
+ if (regnum == -1 || regnum == RISCV_ZERO_REGNUM)
+ regcache->raw_supply_zeroed (RISCV_ZERO_REGNUM);
+
+ if (regnum == -1 || regnum == RISCV_CSR_FFLAGS_REGNUM
+ || regnum == RISCV_CSR_FRM_REGNUM)
+ {
+ int fcsr_regnum = RISCV_CSR_FCSR_REGNUM;
+
+ /* Ensure that FCSR has been read into REGCACHE. */
+ if (regnum != -1)
+ regcache->supply_regset (regset, fcsr_regnum, regs, len);
+
+ /* Grab the FCSR value if it is now in the regcache. We must check
+ the status first as, if the register was not supplied by REGSET,
+ this call will trigger a recursive attempt to fetch the
+ registers. */
+ if (regcache->get_register_status (fcsr_regnum) == REG_VALID)
+ {
+ ULONGEST fcsr_val;
+ regcache->raw_read (fcsr_regnum, &fcsr_val);
+
+ /* Extract the fflags and frm values. */
+ ULONGEST fflags_val = fcsr_val & 0x1f;
+ ULONGEST frm_val = (fcsr_val >> 5) & 0x7;
+
+ /* And supply these if needed. */
+ if (regnum == -1 || regnum == RISCV_CSR_FFLAGS_REGNUM)
+ regcache->raw_supply_integer (RISCV_CSR_FFLAGS_REGNUM,
+ (gdb_byte *) &fflags_val,
+ sizeof (fflags_val),
+ /* is_signed */ false);
+
+ if (regnum == -1 || regnum == RISCV_CSR_FRM_REGNUM)
+ regcache->raw_supply_integer (RISCV_CSR_FRM_REGNUM,
+ (gdb_byte *)&frm_val,
+ sizeof (fflags_val),
+ /* is_signed */ false);
+ }
+ }
+}
+
void _initialize_riscv_tdep ();
void
_initialize_riscv_tdep ()