RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.

* Renamed obsolete UJ/SB types and RVC types, also added CSS/CL(CS) types,

[VALID/EXTRACT/ENCODE macros]
BTYPE_IMM:            Renamed from SBTYPE_IMM.
JTYPE_IMM:            Renamed from UJTYPE_IMM.
CITYPE_IMM:           Renamed from RVC_IMM.
CITYPE_LUI_IMM:       Renamed from RVC_LUI_IMM.
CITYPE_ADDI16SP_IMM:  Renamed from RVC_ADDI16SP_IMM.
CITYPE_LWSP_IMM:      Renamed from RVC_LWSP_IMM.
CITYPE_LDSP_IMM:      Renamed from RVC_LDSP_IMM.
CIWTYPE_IMM:          Renamed from RVC_UIMM8.
CIWTYPE_ADDI4SPN_IMM: Renamed from RVC_ADDI4SPN_IMM.
CSSTYPE_IMM:          Added for .insn without special encoding.
CSSTYPE_SWSP_IMM:     Renamed from RVC_SWSP_IMM.
CSSTYPE_SDSP_IMM:     Renamed from RVC_SDSP_IMM.
CLTYPE_IMM:           Added for .insn without special encoding.
CLTYPE_LW_IMM:        Renamed from RVC_LW_IMM.
CLTYPE_LD_IMM:        Renamed from RVC_LD_IMM.
RVC_SIMM3:            Unused and removed.
CBTYPE_IMM:           Renamed from RVC_B_IMM.
CJTYPE_IMM:           Renamed from RVC_J_IMM.

* Added new operands and removed the unused ones,

C5: Unsigned CL(CS) immediate, added for .insn directive.
C6: Unsigned CSS immediate, added for .insn directive.
Ci: Unused and removed.
C<: Unused and removed.

bfd/
    PR 27158
    * elfnn-riscv.c (perform_relocation): Updated encoding macros.
    (_bfd_riscv_relax_call): Likewise.
    (_bfd_riscv_relax_lui): Likewise.
    * elfxx-riscv.c (howto_table): Likewise.
gas/
    PR 27158
    * config/tc-riscv.c (riscv_ip): Updated encoding macros.
    (md_apply_fix): Likewise.
    (md_convert_frag_branch): Likewise.
    (validate_riscv_insn): Likewise.  Also arranged operands, including
    added C5 and C6 operands, and removed unused Ci and C< operands.
    * doc/c-riscv.texi: Updated and added CSS/CL/CS types.
    * testsuite/gas/riscv/insn.d: Added CSS/CL/CS instructions.
    * testsuite/gas/riscv/insn.s: Likewise.
gdb/
    PR 27158
    * riscv-tdep.c (decode_ci_type_insn): Updated encoding macros.
    (decode_j_type_insn): Likewise.
    (decode_cj_type_insn): Likewise.
    (decode_b_type_insn): Likewise.
    (decode): Likewise.
include/
    PR 27158
    * opcode/riscv.h: Updated encoding macros.
opcodes/
    PR 27158
    * riscv-dis.c (print_insn_args): Updated encoding macros.
    * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
    (match_c_addi16sp): Updated encoding macros.
    (match_c_lui): Likewise.
    (match_c_lui_with_hint): Likewise.
    (match_c_addi4spn): Likewise.
    (match_c_slli): Likewise.
    (match_slli_as_c_slli): Likewise.
    (match_c_slli64): Likewise.
    (match_srxi_as_c_srxi): Likewise.
    (riscv_insn_types): Added .insn css/cl/cs.
sim/
    PR 27158
    * riscv/sim-main.c (execute_i): Updated encoding macros.

1 files changed, 12 insertions, 12 deletions

diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 460746a..7463b0c 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -1399,7 +1399,7 @@ private:
   {
     m_opcode = opcode;
     m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
-    m_imm.s = EXTRACT_RVC_IMM (ival);
+    m_imm.s = EXTRACT_CITYPE_IMM (ival);
   }
 
   /* Helper for DECODE, decode 32-bit S-type instruction.  */
@@ -1449,14 +1449,14 @@ private:
   {
     m_opcode = opcode;
     m_rd = decode_register_index (ival, OP_SH_RD);
-    m_imm.s = EXTRACT_UJTYPE_IMM (ival);
+    m_imm.s = EXTRACT_JTYPE_IMM (ival);
   }
 
   /* Helper for DECODE, decode 32-bit J-type instruction.  */
   void decode_cj_type_insn (enum opcode opcode, ULONGEST ival)
   {
     m_opcode = opcode;
-    m_imm.s = EXTRACT_RVC_J_IMM (ival);
+    m_imm.s = EXTRACT_CJTYPE_IMM (ival);
   }
 
   void decode_b_type_insn (enum opcode opcode, ULONGEST ival)
@@ -1464,14 +1464,14 @@ private:
     m_opcode = opcode;
     m_rs1 = decode_register_index (ival, OP_SH_RS1);
     m_rs2 = decode_register_index (ival, OP_SH_RS2);
-    m_imm.s = EXTRACT_SBTYPE_IMM (ival);
+    m_imm.s = EXTRACT_BTYPE_IMM (ival);
   }
 
   void decode_cb_type_insn (enum opcode opcode, ULONGEST ival)
   {
     m_opcode = opcode;
     m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
-    m_imm.s = EXTRACT_RVC_B_IMM (ival);
+    m_imm.s = EXTRACT_CBTYPE_IMM (ival);
   }
 
   /* Fetch instruction from target memory at ADDR, return the content of
@@ -1629,31 +1629,31 @@ riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc)
 	{
 	  m_opcode = ADDI;
 	  m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD);
-	  m_imm.s = EXTRACT_RVC_ADDI16SP_IMM (ival);
+	  m_imm.s = EXTRACT_CITYPE_ADDI16SP_IMM (ival);
 	}
       else if (is_c_addi4spn_insn (ival))
 	{
 	  m_opcode = ADDI;
 	  m_rd = decode_register_index_short (ival, OP_SH_CRS2S);
 	  m_rs1 = RISCV_SP_REGNUM;
-	  m_imm.s = EXTRACT_RVC_ADDI4SPN_IMM (ival);
+	  m_imm.s = EXTRACT_CIWTYPE_ADDI4SPN_IMM (ival);
 	}
       else if (is_c_lui_insn (ival))
 	{
 	  m_opcode = LUI;
 	  m_rd = decode_register_index (ival, OP_SH_CRS1S);
-	  m_imm.s = EXTRACT_RVC_LUI_IMM (ival);
+	  m_imm.s = EXTRACT_CITYPE_LUI_IMM (ival);
 	}
       /* C_SD and C_FSW have the same opcode.  C_SD is RV64 and RV128 only,
 	 and C_FSW is RV32 only.  */
       else if (xlen != 4 && is_c_sd_insn (ival))
-	decode_cs_type_insn (SD, ival, EXTRACT_RVC_LD_IMM (ival));
+	decode_cs_type_insn (SD, ival, EXTRACT_CLTYPE_LD_IMM (ival));
       else if (is_c_sw_insn (ival))
-	decode_cs_type_insn (SW, ival, EXTRACT_RVC_LW_IMM (ival));
+	decode_cs_type_insn (SW, ival, EXTRACT_CLTYPE_LW_IMM (ival));
       else if (is_c_swsp_insn (ival))
-	decode_css_type_insn (SW, ival, EXTRACT_RVC_SWSP_IMM (ival));
+	decode_css_type_insn (SW, ival, EXTRACT_CSSTYPE_SWSP_IMM (ival));
       else if (xlen != 4 && is_c_sdsp_insn (ival))
-	decode_css_type_insn (SD, ival, EXTRACT_RVC_SDSP_IMM (ival));
+	decode_css_type_insn (SD, ival, EXTRACT_CSSTYPE_SDSP_IMM (ival));
       /* C_JR and C_MV have the same opcode.  If RS2 is 0, then this is a C_JR.
 	 So must try to match C_JR first as it ahs more bits in mask.  */
       else if (is_c_jr_insn (ival))