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| author | Andrew Cagney <cagney@redhat.com> | 2002-11-13 17:59:40 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 2002-11-13 17:59:40 +0000 |
| commit | 2d28509afbfaaf187508a0c85ae3fb98d96d185b (patch) | |
| tree | dca4c352d87223e637b4749987440db0fca09200 /gdb/regcache.h | |
| parent | 067df2e5b48bf819c7edc60044bdde38b5f2ece7 (diff) | |
| download | gdb-2d28509afbfaaf187508a0c85ae3fb98d96d185b.zip gdb-2d28509afbfaaf187508a0c85ae3fb98d96d185b.tar.gz gdb-2d28509afbfaaf187508a0c85ae3fb98d96d185b.tar.bz2 | |
2002-11-13 Andrew Cagney <cagney@redhat.com>
* regcache.c (struct regcache): Replace passthough_p with
readonly_p.
(regcache_xmalloc): Initialize readonly_p.
(build_regcache): Initialize readonly_p.
(regcache_save): New function.
(regcache_restore): New function.
(regcache_cpy): Re-implement using regcache_save and
regcache_restore.
(regcache_raw_read): Update.
(regcache_cooked_read): When a read-only cache, checked for cached
pseudo register values.
(regcache_raw_write): Assert that the cache is not read-only.
Remove code handling a non-passthrough cache.
* regcache.h (regcache_save): Declare.
(regcache_restore): Declare.
Diffstat (limited to 'gdb/regcache.h')
| -rw-r--r-- | gdb/regcache.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/gdb/regcache.h b/gdb/regcache.h index ad70298..a1ea2fa 100644 --- a/gdb/regcache.h +++ b/gdb/regcache.h @@ -134,6 +134,16 @@ extern int max_register_size (struct gdbarch *gdbarch); extern char *registers; +/* Save/restore a register cache. The registers saved/restored is + determined by the save_reggroup and restore_reggroup (although you + can't restore a register that wasn't saved as well :-). You can + only save to a read-only cache (default from regcache_xmalloc()) + from a live cache and you can only restore from a read-only cache + to a live cache. */ + +extern void regcache_save (struct regcache *dst, struct regcache *src); +extern void regcache_restore (struct regcache *dst, struct regcache *src); + /* Copy/duplicate the contents of a register cache. By default, the operation is pass-through. Writes to DST and reads from SRC will go through to the target. |