Sync up x86-gcc-cpuid.h with cpuid.h from gcc-6 branch.

Pedro suggested a separate patch synching with GCCs cpuid.h
instead of just adding new bits for PKU feature.

 gdb/Changelog:
     2016-11-14  Michael Sturm  <michael.sturm@intel.com>

          * nat/x86-gcc-cpuid.h: Replace with copy of cpuid.h
            from gcc-6 branch.

Change-Id: I16f8f7f2d0aa7c2e815701d15ed831a6c6b33d21
Signed-off-by: Michael Sturm <michael.sturm@intel.com>

1 files changed, 50 insertions, 58 deletions

diff --git a/gdb/nat/x86-gcc-cpuid.h b/gdb/nat/x86-gcc-cpuid.h
index d800c82..d412c42 100644
--- a/gdb/nat/x86-gcc-cpuid.h
+++ b/gdb/nat/x86-gcc-cpuid.h
@@ -1,5 +1,5 @@
 /*
- * Helper cpuid.h file copied from gcc-4.8.0.  Code in gdb should not
+ * Helper cpuid.h file copied from gcc-6.0.0.  Code in gdb should not
  * include this directly, but pull in x86-cpuid.h and use that func.
  */
 /*
@@ -61,31 +61,56 @@
 #define bit_LWP 	(1 << 15)
 #define bit_FMA4        (1 << 16)
 #define bit_TBM         (1 << 21)
+#define bit_MWAITX      (1 << 29)
 
 /* %edx */
+#define bit_AVX5124VNNIW (1 << 2)
+#define bit_AVX5124FMAPS (1 << 3)
 #define bit_MMXEXT	(1 << 22)
 #define bit_LM		(1 << 29)
 #define bit_3DNOWP	(1 << 30)
 #define bit_3DNOW	(1 << 31)
 
+/* %ebx.  */
+#define bit_CLZERO	(1 << 0)
+
 /* Extended Features (%eax == 7) */
+/* %ebx */
 #define bit_FSGSBASE	(1 << 0)
 #define bit_BMI	(1 << 3)
 #define bit_HLE	(1 << 4)
 #define bit_AVX2	(1 << 5)
 #define bit_BMI2	(1 << 8)
 #define bit_RTM	(1 << 11)
+#define bit_MPX	(1 << 14)
 #define bit_AVX512F	(1 << 16)
-#define bit_MPX (1 << 14)
+#define bit_AVX512DQ	(1 << 17)
 #define bit_RDSEED	(1 << 18)
 #define bit_ADX	(1 << 19)
+#define bit_AVX512IFMA	(1 << 21)
+#define bit_CLFLUSHOPT	(1 << 23)
+#define bit_CLWB	(1 << 24)
 #define bit_AVX512PF	(1 << 26)
 #define bit_AVX512ER	(1 << 27)
 #define bit_AVX512CD	(1 << 28)
 #define bit_SHA		(1 << 29)
+#define bit_AVX512BW	(1 << 30)
+#define bit_AVX512VL	(1 << 31)
+
+/* %ecx */
+#define bit_PREFETCHWT1	  (1 << 0)
+#define bit_AVX512VBMI	(1 << 1)
+#define bit_PKU	(1 << 3)
+#define bit_OSPKE	(1 << 4)
+
+/* XFEATURE_ENABLED_MASK register bits (%eax == 13, %ecx == 0) */
+#define bit_BNDREGS     (1 << 3)
+#define bit_BNDCSR      (1 << 4)
 
 /* Extended State Enumeration Sub-leaf (%eax == 13, %ecx == 1) */
 #define bit_XSAVEOPT	(1 << 0)
+#define bit_XSAVEC	(1 << 1)
+#define bit_XSAVES	(1 << 3)
 
 /* Signatures for different CPU implementations as returned in uses
    of cpuid with level 0.  */
@@ -141,55 +166,6 @@
 #define signature_VORTEX_ecx	0x436f5320
 #define signature_VORTEX_edx	0x36387865
 
-#if defined(__i386__) && defined(__PIC__)
-/* %ebx may be the PIC register.  */
-#if __GNUC__ >= 3
-#define __cpuid(level, a, b, c, d)			\
-  __asm__ ("xchg{l}\t{%%}ebx, %k1\n\t"			\
-	   "cpuid\n\t"					\
-	   "xchg{l}\t{%%}ebx, %k1\n\t"			\
-	   : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)	\
-	   : "0" (level))
-
-#define __cpuid_count(level, count, a, b, c, d)		\
-  __asm__ ("xchg{l}\t{%%}ebx, %k1\n\t"			\
-	   "cpuid\n\t"					\
-	   "xchg{l}\t{%%}ebx, %k1\n\t"			\
-	   : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)	\
-	   : "0" (level), "2" (count))
-#else
-/* Host GCCs older than 3.0 weren't supporting Intel asm syntax
-   nor alternatives in i386 code.  */
-#define __cpuid(level, a, b, c, d)			\
-  __asm__ ("xchgl\t%%ebx, %k1\n\t"			\
-	   "cpuid\n\t"					\
-	   "xchgl\t%%ebx, %k1\n\t"			\
-	   : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)	\
-	   : "0" (level))
-
-#define __cpuid_count(level, count, a, b, c, d)		\
-  __asm__ ("xchgl\t%%ebx, %k1\n\t"			\
-	   "cpuid\n\t"					\
-	   "xchgl\t%%ebx, %k1\n\t"			\
-	   : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)	\
-	   : "0" (level), "2" (count))
-#endif
-#elif defined(__x86_64__) && (defined(__code_model_medium__) || defined(__code_model_large__)) && defined(__PIC__)
-/* %rbx may be the PIC register.  */
-#define __cpuid(level, a, b, c, d)			\
-  __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t"			\
-	   "cpuid\n\t"					\
-	   "xchg{q}\t{%%}rbx, %q1\n\t"			\
-	   : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)	\
-	   : "0" (level))
-
-#define __cpuid_count(level, count, a, b, c, d)		\
-  __asm__ ("xchg{q}\t{%%}rbx, %q1\n\t"			\
-	   "cpuid\n\t"					\
-	   "xchg{q}\t{%%}rbx, %q1\n\t"			\
-	   : "=a" (a), "=&r" (b), "=c" (c), "=d" (d)	\
-	   : "0" (level), "2" (count))
-#else
 #define __cpuid(level, a, b, c, d)			\
   __asm__ ("cpuid\n\t"					\
 	   : "=a" (a), "=b" (b), "=c" (c), "=d" (d)	\
@@ -199,7 +175,7 @@
   __asm__ ("cpuid\n\t"					\
 	   : "=a" (a), "=b" (b), "=c" (c), "=d" (d)	\
 	   : "0" (level), "2" (count))
-#endif
+
 
 /* Return highest supported input value for cpuid instruction.  ext can
    be either 0x0 or 0x8000000 to return highest supported value for
@@ -258,21 +234,37 @@ __get_cpuid_max (unsigned int __ext, unsigned int *__sig)
   return __eax;
 }
 
-/* Return cpuid data for requested cpuid level, as found in returned
+/* Return cpuid data for requested cpuid leaf, as found in returned
    eax, ebx, ecx and edx registers.  The function checks if cpuid is
    supported and returns 1 for valid cpuid information or 0 for
-   unsupported cpuid level.  All pointers are required to be non-null.  */
+   unsupported cpuid leaf.  All pointers are required to be non-null.  */
 
 static __inline int
-__get_cpuid (unsigned int __level,
+__get_cpuid (unsigned int __leaf,
 	     unsigned int *__eax, unsigned int *__ebx,
 	     unsigned int *__ecx, unsigned int *__edx)
 {
-  unsigned int __ext = __level & 0x80000000;
+  unsigned int __ext = __leaf & 0x80000000;
+
+  if (__get_cpuid_max (__ext, 0) < __leaf)
+    return 0;
+
+  __cpuid (__leaf, *__eax, *__ebx, *__ecx, *__edx);
+  return 1;
+}
+
+/* Same as above, but sub-leaf can be specified.  */
+
+static __inline int
+__get_cpuid_count (unsigned int __leaf, unsigned int __subleaf,
+		   unsigned int *__eax, unsigned int *__ebx,
+		   unsigned int *__ecx, unsigned int *__edx)
+{
+  unsigned int __ext = __leaf & 0x80000000;
 
-  if (__get_cpuid_max (__ext, 0) < __level)
+  if (__get_cpuid_max (__ext, 0) < __leaf)
     return 0;
 
-  __cpuid (__level, *__eax, *__ebx, *__ecx, *__edx);
+  __cpuid_count (__leaf, __subleaf, *__eax, *__ebx, *__ecx, *__edx);
   return 1;
 }