Move common aarch64 HW breakpoint/watchpoint code to nat/

When I look at test fails related to watchpoint on aarch64-linux,
I find there are some code duplicates between GDB and GDBserver.
This patch is to move some of them to a nat/aarch64-linux-hw-point.{h,c}.

The only change I do is about the dr_changed_t typedef, which was
ULONGEST in GDB and 'unsigned long long' in GDBserver.  Each bit
of dr_changed_t represents a status of each HW breakpoint or
watchpoint register, and the max number of HW breakpoint or watchpoint
registers is 16, so the width of 'unsigned long long' is sufficient.

gdb:

2015-07-17  Yao Qi  <yao.qi@linaro.org>

	* Makefile.in (HFILES_NO_SRCDIR): Add
	nat/aarch64-linux-hw-point.h.
	(aarch64-linux-hw-point.o): New rule.
	* nat/aarch64-linux-hw-point.h: New file.
	* nat/aarch64-linux-hw-point.c: New file.
	* aarch64-linux-nat.c: Include nat/aarch64-linux-hw-point.h.
	(AARCH64_HBP_MAX_NUM): Move to nat/aarch64-linux-hw-point.h.
	(AARCH64_HWP_MAX_NUM, AARCH64_HBP_ALIGNMENT): Likewise.
	(AARCH64_HWP_ALIGNMENT): Likewise.
	(AARCH64_HWP_MAX_LEN_PER_REG): Likewise.
	(AARCH64_DEBUG_NUM_SLOTS, AARCH64_DEBUG_ARCH): Likewise.
	(AARCH64_DEBUG_ARCH_V8, DR_MARK_ALL_CHANGED): Likewise.
	(DR_MARK_N_CHANGED, DR_CLEAR_CHANGED): Likewise.
	(DR_HAS_CHANGED, DR_N_HAS_CHANGE): Likewise.
	(aarch64_num_bp_regs, aarch64_num_wp_regs): Likewise.
	(struct aarch64_debug_reg_state): Likewise.
	(struct arch_lwp_info):	Likewise.
	(aarch64_linux_set_debug_regs): Likewise.
	(aarch64_notify_debug_reg_change): Remove static.
	(aarch64_align_watchpoint): Likewise.
	(DR_CONTROL_ENABLED, DR_CONTROL_LENGTH): Likewise.
	(aarch64_watchpoint_length): Likewise.
	(aarch64_point_encode_ctrl_reg): Likewise
	(aarch64_point_is_aligned): Likewise.
	(aarch64_dr_state_insert_one_point): Likewise.
	(aarch64_dr_state_remove_one_point): Likewise.
	(aarch64_handle_breakpoint): Likewise.
	(aarch64_handle_aligned_watchpoint): Likewise.
	(aarch64_handle_unaligned_watchpoint): Likewise.
	(aarch64_handle_watchpoint): Likewise.
	* config/aarch64/linux.mh (NAT_FILE): Add
	aarch64-linux-hw-point.o.

gdb/gdbserver:

2015-07-17  Yao Qi  <yao.qi@linaro.org>

	* Makefile.in (aarch64-linux-hw-point.o): New rule.
	* configure.srv (srv_tgtobj): Append aarch64-linux-hw-point.o.
	* linux-aarch64-low.c: Include nat/aarch64-linux-hw-point.h.
	(AARCH64_HBP_MAX_NUM): Move to nat/aarch64-linux-hw-point.h.
	(AARCH64_HWP_MAX_NUM, AARCH64_HBP_ALIGNMENT): Likewise.
	(AARCH64_HWP_ALIGNMENT): Likewise.
	(AARCH64_HWP_MAX_LEN_PER_REG): Likewise.
	(AARCH64_DEBUG_NUM_SLOTS, AARCH64_DEBUG_ARCH): Likewise.
	(aarch64_num_bp_regs, aarch64_num_wp_regs): Likewise.
	(AARCH64_DEBUG_ARCH_V8, DR_MARK_ALL_CHANGED): Likewise.
	(DR_MARK_N_CHANGED, DR_CLEAR_CHANGED): Likewise.
	(DR_HAS_CHANGED, DR_N_HAS_CHANGE): Likewise.
	(struct aarch64_debug_reg_state): Likewise.
	(struct arch_lwp_info):	Likewise.
	(aarch64_align_watchpoint): Likewise.
	(DR_CONTROL_ENABLED, DR_CONTROL_LENGTH): Likewise.
	(aarch64_watchpoint_length): Likewise.
	(aarch64_point_encode_ctrl_reg): Likewise
	(aarch64_point_is_aligned): Likewise.
	(aarch64_align_watchpoint): Likewise.
	(aarch64_linux_set_debug_regs):
	(aarch64_dr_state_insert_one_point): Likewise.
	(aarch64_dr_state_remove_one_point): Likewise.
	(aarch64_handle_breakpoint): Likewise.
	(aarch64_handle_aligned_watchpoint): Likewise.
	(aarch64_handle_unaligned_watchpoint): Likewise.
	(aarch64_handle_watchpoint): Likewise.

1 files changed, 505 insertions, 0 deletions

diff --git a/gdb/nat/aarch64-linux-hw-point.c b/gdb/nat/aarch64-linux-hw-point.c
new file mode 100644
index 0000000..ded4a19
--- /dev/null
+++ b/gdb/nat/aarch64-linux-hw-point.c
@@ -0,0 +1,505 @@
+/* Copyright (C) 2009-2015 Free Software Foundation, Inc.
+   Contributed by ARM Ltd.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#include "common-defs.h"
+#include "break-common.h"
+#include "aarch64-linux-hw-point.h"
+
+#include <sys/uio.h>
+#include <asm/ptrace.h>
+#include <sys/ptrace.h>
+#include <elf.h>
+
+/* Number of hardware breakpoints/watchpoints the target supports.
+   They are initialized with values obtained via the ptrace calls
+   with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively.  */
+
+int aarch64_num_bp_regs;
+int aarch64_num_wp_regs;
+
+/* Utility function that returns the length in bytes of a watchpoint
+   according to the content of a hardware debug control register CTRL.
+   Note that the kernel currently only supports the following Byte
+   Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means
+   that for a hardware watchpoint, its valid length can only be 1
+   byte, 2 bytes, 4 bytes or 8 bytes.  */
+
+unsigned int
+aarch64_watchpoint_length (unsigned int ctrl)
+{
+  switch (DR_CONTROL_LENGTH (ctrl))
+    {
+    case 0x01:
+      return 1;
+    case 0x03:
+      return 2;
+    case 0x0f:
+      return 4;
+    case 0xff:
+      return 8;
+    default:
+      return 0;
+    }
+}
+
+/* Given the hardware breakpoint or watchpoint type TYPE and its
+   length LEN, return the expected encoding for a hardware
+   breakpoint/watchpoint control register.  */
+
+static unsigned int
+aarch64_point_encode_ctrl_reg (enum target_hw_bp_type type, int len)
+{
+  unsigned int ctrl, ttype;
+
+  /* type */
+  switch (type)
+    {
+    case hw_write:
+      ttype = 2;
+      break;
+    case hw_read:
+      ttype = 1;
+      break;
+    case hw_access:
+      ttype = 3;
+      break;
+    case hw_execute:
+      ttype = 0;
+      break;
+    default:
+      perror_with_name (_("Unrecognized breakpoint/watchpoint type"));
+    }
+
+  ctrl = ttype << 3;
+
+  /* length bitmask */
+  ctrl |= ((1 << len) - 1) << 5;
+  /* enabled at el0 */
+  ctrl |= (2 << 1) | 1;
+
+  return ctrl;
+}
+
+/* Addresses to be written to the hardware breakpoint and watchpoint
+   value registers need to be aligned; the alignment is 4-byte and
+   8-type respectively.  Linux kernel rejects any non-aligned address
+   it receives from the related ptrace call.  Furthermore, the kernel
+   currently only supports the following Byte Address Select (BAS)
+   values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware
+   watchpoint to be accepted by the kernel (via ptrace call), its
+   valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes.
+   Despite these limitations, the unaligned watchpoint is supported in
+   this port.
+
+   Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise.  */
+
+static int
+aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len)
+{
+  unsigned int alignment = is_watchpoint ? AARCH64_HWP_ALIGNMENT
+    : AARCH64_HBP_ALIGNMENT;
+
+  if (addr & (alignment - 1))
+    return 0;
+
+  if (len != 8 && len != 4 && len != 2 && len != 1)
+    return 0;
+
+  return 1;
+}
+
+/* Given the (potentially unaligned) watchpoint address in ADDR and
+   length in LEN, return the aligned address and aligned length in
+   *ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively.  The returned
+   aligned address and length will be valid values to write to the
+   hardware watchpoint value and control registers.
+
+   The given watchpoint may get truncated if more than one hardware
+   register is needed to cover the watched region.  *NEXT_ADDR_P
+   and *NEXT_LEN_P, if non-NULL, will return the address and length
+   of the remaining part of the watchpoint (which can be processed
+   by calling this routine again to generate another aligned address
+   and length pair.
+
+   Essentially, unaligned watchpoint is achieved by minimally
+   enlarging the watched area to meet the alignment requirement, and
+   if necessary, splitting the watchpoint over several hardware
+   watchpoint registers.  The trade-off is that there will be
+   false-positive hits for the read-type or the access-type hardware
+   watchpoints; for the write type, which is more commonly used, there
+   will be no such issues, as the higher-level breakpoint management
+   in gdb always examines the exact watched region for any content
+   change, and transparently resumes a thread from a watchpoint trap
+   if there is no change to the watched region.
+
+   Another limitation is that because the watched region is enlarged,
+   the watchpoint fault address returned by
+   aarch64_stopped_data_address may be outside of the original watched
+   region, especially when the triggering instruction is accessing a
+   larger region.  When the fault address is not within any known
+   range, watchpoints_triggered in gdb will get confused, as the
+   higher-level watchpoint management is only aware of original
+   watched regions, and will think that some unknown watchpoint has
+   been triggered.  In such a case, gdb may stop without displaying
+   any detailed information.
+
+   Once the kernel provides the full support for Byte Address Select
+   (BAS) in the hardware watchpoint control register, these
+   limitations can be largely relaxed with some further work.  */
+
+static void
+aarch64_align_watchpoint (CORE_ADDR addr, int len, CORE_ADDR *aligned_addr_p,
+			  int *aligned_len_p, CORE_ADDR *next_addr_p,
+			  int *next_len_p)
+{
+  int aligned_len;
+  unsigned int offset;
+  CORE_ADDR aligned_addr;
+  const unsigned int alignment = AARCH64_HWP_ALIGNMENT;
+  const unsigned int max_wp_len = AARCH64_HWP_MAX_LEN_PER_REG;
+
+  /* As assumed by the algorithm.  */
+  gdb_assert (alignment == max_wp_len);
+
+  if (len <= 0)
+    return;
+
+  /* Address to be put into the hardware watchpoint value register
+     must be aligned.  */
+  offset = addr & (alignment - 1);
+  aligned_addr = addr - offset;
+
+  gdb_assert (offset >= 0 && offset < alignment);
+  gdb_assert (aligned_addr >= 0 && aligned_addr <= addr);
+  gdb_assert (offset + len > 0);
+
+  if (offset + len >= max_wp_len)
+    {
+      /* Need more than one watchpoint registers; truncate it at the
+	 alignment boundary.  */
+      aligned_len = max_wp_len;
+      len -= (max_wp_len - offset);
+      addr += (max_wp_len - offset);
+      gdb_assert ((addr & (alignment - 1)) == 0);
+    }
+  else
+    {
+      /* Find the smallest valid length that is large enough to
+	 accommodate this watchpoint.  */
+      static const unsigned char
+	aligned_len_array[AARCH64_HWP_MAX_LEN_PER_REG] =
+	{ 1, 2, 4, 4, 8, 8, 8, 8 };
+
+      aligned_len = aligned_len_array[offset + len - 1];
+      addr += len;
+      len = 0;
+    }
+
+  if (aligned_addr_p)
+    *aligned_addr_p = aligned_addr;
+  if (aligned_len_p)
+    *aligned_len_p = aligned_len;
+  if (next_addr_p)
+    *next_addr_p = addr;
+  if (next_len_p)
+    *next_len_p = len;
+}
+
+/* Record the insertion of one breakpoint/watchpoint, as represented
+   by ADDR and CTRL, in the process' arch-specific data area *STATE.  */
+
+static int
+aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state *state,
+				   enum target_hw_bp_type type,
+				   CORE_ADDR addr, int len)
+{
+  int i, idx, num_regs, is_watchpoint;
+  unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
+  CORE_ADDR *dr_addr_p;
+
+  /* Set up state pointers.  */
+  is_watchpoint = (type != hw_execute);
+  gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
+  if (is_watchpoint)
+    {
+      num_regs = aarch64_num_wp_regs;
+      dr_addr_p = state->dr_addr_wp;
+      dr_ctrl_p = state->dr_ctrl_wp;
+      dr_ref_count = state->dr_ref_count_wp;
+    }
+  else
+    {
+      num_regs = aarch64_num_bp_regs;
+      dr_addr_p = state->dr_addr_bp;
+      dr_ctrl_p = state->dr_ctrl_bp;
+      dr_ref_count = state->dr_ref_count_bp;
+    }
+
+  ctrl = aarch64_point_encode_ctrl_reg (type, len);
+
+  /* Find an existing or free register in our cache.  */
+  idx = -1;
+  for (i = 0; i < num_regs; ++i)
+    {
+      if ((dr_ctrl_p[i] & 1) == 0)
+	{
+	  gdb_assert (dr_ref_count[i] == 0);
+	  idx = i;
+	  /* no break; continue hunting for an exising one.  */
+	}
+      else if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
+	{
+	  gdb_assert (dr_ref_count[i] != 0);
+	  idx = i;
+	  break;
+	}
+    }
+
+  /* No space.  */
+  if (idx == -1)
+    return -1;
+
+  /* Update our cache.  */
+  if ((dr_ctrl_p[idx] & 1) == 0)
+    {
+      /* new entry */
+      dr_addr_p[idx] = addr;
+      dr_ctrl_p[idx] = ctrl;
+      dr_ref_count[idx] = 1;
+      /* Notify the change.  */
+      aarch64_notify_debug_reg_change (state, is_watchpoint, idx);
+    }
+  else
+    {
+      /* existing entry */
+      dr_ref_count[idx]++;
+    }
+
+  return 0;
+}
+
+/* Record the removal of one breakpoint/watchpoint, as represented by
+   ADDR and CTRL, in the process' arch-specific data area *STATE.  */
+
+static int
+aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state *state,
+				   enum target_hw_bp_type type,
+				   CORE_ADDR addr, int len)
+{
+  int i, num_regs, is_watchpoint;
+  unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
+  CORE_ADDR *dr_addr_p;
+
+  /* Set up state pointers.  */
+  is_watchpoint = (type != hw_execute);
+  gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
+  if (is_watchpoint)
+    {
+      num_regs = aarch64_num_wp_regs;
+      dr_addr_p = state->dr_addr_wp;
+      dr_ctrl_p = state->dr_ctrl_wp;
+      dr_ref_count = state->dr_ref_count_wp;
+    }
+  else
+    {
+      num_regs = aarch64_num_bp_regs;
+      dr_addr_p = state->dr_addr_bp;
+      dr_ctrl_p = state->dr_ctrl_bp;
+      dr_ref_count = state->dr_ref_count_bp;
+    }
+
+  ctrl = aarch64_point_encode_ctrl_reg (type, len);
+
+  /* Find the entry that matches the ADDR and CTRL.  */
+  for (i = 0; i < num_regs; ++i)
+    if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
+      {
+	gdb_assert (dr_ref_count[i] != 0);
+	break;
+      }
+
+  /* Not found.  */
+  if (i == num_regs)
+    return -1;
+
+  /* Clear our cache.  */
+  if (--dr_ref_count[i] == 0)
+    {
+      /* Clear the enable bit.  */
+      ctrl &= ~1;
+      dr_addr_p[i] = 0;
+      dr_ctrl_p[i] = ctrl;
+      /* Notify the change.  */
+      aarch64_notify_debug_reg_change (state, is_watchpoint, i);
+    }
+
+  return 0;
+}
+
+int
+aarch64_handle_breakpoint (enum target_hw_bp_type type, CORE_ADDR addr,
+			   int len, int is_insert,
+			   struct aarch64_debug_reg_state *state)
+{
+  /* The hardware breakpoint on AArch64 should always be 4-byte
+     aligned.  */
+  if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr, len))
+    return -1;
+
+  if (is_insert)
+    return aarch64_dr_state_insert_one_point (state, type, addr, len);
+  else
+    return aarch64_dr_state_remove_one_point (state, type, addr, len);
+}
+
+/* This is essentially the same as aarch64_handle_breakpoint, apart
+   from that it is an aligned watchpoint to be handled.  */
+
+static int
+aarch64_handle_aligned_watchpoint (enum target_hw_bp_type type,
+				   CORE_ADDR addr, int len, int is_insert,
+				   struct aarch64_debug_reg_state *state)
+{
+  if (is_insert)
+    return aarch64_dr_state_insert_one_point (state, type, addr, len);
+  else
+    return aarch64_dr_state_remove_one_point (state, type, addr, len);
+}
+
+/* Insert/remove unaligned watchpoint by calling
+   aarch64_align_watchpoint repeatedly until the whole watched region,
+   as represented by ADDR and LEN, has been properly aligned and ready
+   to be written to one or more hardware watchpoint registers.
+   IS_INSERT indicates whether this is an insertion or a deletion.
+   Return 0 if succeed.  */
+
+static int
+aarch64_handle_unaligned_watchpoint (enum target_hw_bp_type type,
+				     CORE_ADDR addr, int len, int is_insert,
+				     struct aarch64_debug_reg_state *state)
+{
+  while (len > 0)
+    {
+      CORE_ADDR aligned_addr;
+      int aligned_len, ret;
+
+      aarch64_align_watchpoint (addr, len, &aligned_addr, &aligned_len,
+				&addr, &len);
+
+      if (is_insert)
+	ret = aarch64_dr_state_insert_one_point (state, type, aligned_addr,
+						 aligned_len);
+      else
+	ret = aarch64_dr_state_remove_one_point (state, type, aligned_addr,
+						 aligned_len);
+
+      if (show_debug_regs)
+	debug_printf (
+"handle_unaligned_watchpoint: is_insert: %d\n"
+"                             aligned_addr: %s, aligned_len: %d\n"
+"                                next_addr: %s,    next_len: %d\n",
+is_insert, core_addr_to_string_nz (aligned_addr), aligned_len,
+core_addr_to_string_nz (addr), len);
+
+      if (ret != 0)
+	return ret;
+    }
+
+  return 0;
+}
+
+int
+aarch64_handle_watchpoint (enum target_hw_bp_type type, CORE_ADDR addr,
+			   int len, int is_insert,
+			   struct aarch64_debug_reg_state *state)
+{
+  if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr, len))
+    return aarch64_handle_aligned_watchpoint (type, addr, len, is_insert,
+					      state);
+  else
+    return aarch64_handle_unaligned_watchpoint (type, addr, len, is_insert,
+						state);
+}
+
+/* Call ptrace to set the thread TID's hardware breakpoint/watchpoint
+   registers with data from *STATE.  */
+
+void
+aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state *state,
+			      int tid, int watchpoint)
+{
+  int i, count;
+  struct iovec iov;
+  struct user_hwdebug_state regs;
+  const CORE_ADDR *addr;
+  const unsigned int *ctrl;
+
+  memset (&regs, 0, sizeof (regs));
+  iov.iov_base = &regs;
+  count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs;
+  addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp;
+  ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp;
+  if (count == 0)
+    return;
+  iov.iov_len = (offsetof (struct user_hwdebug_state, dbg_regs[count - 1])
+		 + sizeof (regs.dbg_regs [count - 1]));
+
+  for (i = 0; i < count; i++)
+    {
+      regs.dbg_regs[i].addr = addr[i];
+      regs.dbg_regs[i].ctrl = ctrl[i];
+    }
+
+  if (ptrace (PTRACE_SETREGSET, tid,
+	      watchpoint ? NT_ARM_HW_WATCH : NT_ARM_HW_BREAK,
+	      (void *) &iov))
+    error (_("Unexpected error setting hardware debug registers"));
+}
+
+/* Print the values of the cached breakpoint/watchpoint registers.  */
+
+void
+aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state,
+			      const char *func, CORE_ADDR addr,
+			      int len, enum target_hw_bp_type type)
+{
+  int i;
+
+  debug_printf ("%s", func);
+  if (addr || len)
+    debug_printf (" (addr=0x%08lx, len=%d, type=%s)",
+		  (unsigned long) addr, len,
+		  type == hw_write ? "hw-write-watchpoint"
+		  : (type == hw_read ? "hw-read-watchpoint"
+		     : (type == hw_access ? "hw-access-watchpoint"
+			: (type == hw_execute ? "hw-breakpoint"
+			   : "??unknown??"))));
+  debug_printf (":\n");
+
+  debug_printf ("\tBREAKPOINTs:\n");
+  for (i = 0; i < aarch64_num_bp_regs; i++)
+    debug_printf ("\tBP%d: addr=%s, ctrl=0x%08x, ref.count=%d\n",
+		  i, core_addr_to_string_nz (state->dr_addr_bp[i]),
+		  state->dr_ctrl_bp[i], state->dr_ref_count_bp[i]);
+
+  debug_printf ("\tWATCHPOINTs:\n");
+  for (i = 0; i < aarch64_num_wp_regs; i++)
+    debug_printf ("\tWP%d: addr=%s, ctrl=0x%08x, ref.count=%d\n",
+		  i, core_addr_to_string_nz (state->dr_addr_wp[i]),
+		  state->dr_ctrl_wp[i], state->dr_ref_count_wp[i]);
+}