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| author | David Anderson <davea@sgi.com> | 2000-10-23 22:49:29 +0000 |
|---|---|---|
| committer | David Anderson <davea@sgi.com> | 2000-10-23 22:49:29 +0000 |
| commit | e26cc3490a00a58329c61e33afd8e682e449b475 (patch) | |
| tree | cce09976de237e6ae6114168cd4e6414b94f5ebb /gdb/mips-tdep.c | |
| parent | 59666b35a830eed6cf0871b0cdcc284d8afcc0ed (diff) | |
| download | gdb-e26cc3490a00a58329c61e33afd8e682e449b475.zip gdb-e26cc3490a00a58329c61e33afd8e682e449b475.tar.gz gdb-e26cc3490a00a58329c61e33afd8e682e449b475.tar.bz2 | |
Corrected spelling errors in comments
Diffstat (limited to 'gdb/mips-tdep.c')
| -rw-r--r-- | gdb/mips-tdep.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c index 20d5446..cf48ced 100644 --- a/gdb/mips-tdep.c +++ b/gdb/mips-tdep.c @@ -819,7 +819,7 @@ mips32_next_pc (CORE_ADDR pc) } /* mips32_next_pc */ /* Decoding the next place to set a breakpoint is irregular for the - mips 16 variant, but fortunatly, there fewer instructions. We have to cope + mips 16 variant, but fortunately, there fewer instructions. We have to cope ith extensions for 16 bit instructions and a pair of actual 32 bit instructions. We dont want to set a single step instruction on the extend instruction either. |