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| author | Yao Qi <yao.qi@linaro.org> | 2016-09-16 14:58:31 +0100 |
|---|---|---|
| committer | Yao Qi <yao.qi@linaro.org> | 2016-09-21 12:45:51 +0100 |
| commit | 61f97a2f940e36d4b4c87ef5b28a49e6834f8e68 (patch) | |
| tree | c1b65a97aa5e2798446fa7b91e8b46dcb7763bbe /gdb/m32r-linux-tdep.c | |
| parent | 79c7eab965f3c183ee7417a889c5ef7591be0f36 (diff) | |
| download | gdb-61f97a2f940e36d4b4c87ef5b28a49e6834f8e68.zip gdb-61f97a2f940e36d4b4c87ef5b28a49e6834f8e68.tar.gz gdb-61f97a2f940e36d4b4c87ef5b28a49e6834f8e68.tar.bz2 | |
Keep reserved bits in CPSR on write
In patch https://sourceware.org/ml/gdb-patches/2016-04/msg00529.html
I cleared reserved bits when reading CPSR. It makes a problem that
these bits (zero) are written back to kernel through ptrace, and it
changes the state of the processor on some recent kernel, which is
unexpected.
In this patch, I keep these reserved bits when write CPSR back to
hardware.
gdb:
2016-09-21 Yao Qi <yao.qi@linaro.org>
* aarch32-linux-nat.c (aarch32_gp_regcache_collect): Keep
bits 20 to 23.
gdb/gdbserver:
2016-09-21 Yao Qi <yao.qi@linaro.org>
* linux-aarch32-low.c (arm_fill_gregset): Keep bits 20 to
23.
Diffstat (limited to 'gdb/m32r-linux-tdep.c')
0 files changed, 0 insertions, 0 deletions