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authorSimon Marchi <simon.marchi@polymtl.ca>2021-11-15 11:29:39 -0500
committerSimon Marchi <simon.marchi@polymtl.ca>2021-11-15 11:29:39 -0500
commit345bd07cce33565f1cd66acabdaf387ca3a7ccb3 (patch)
treebfa86d2102817e06235193c865d2580e802d0a1a /gdb/i386-tdep.h
parenteae06bb301512a21277dd48a4bff025c4dceda9e (diff)
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gdb: fix gdbarch_tdep ODR violation
I would like to be able to use non-trivial types in gdbarch_tdep types. This is not possible at the moment (in theory), because of the one definition rule. To allow it, rename all gdbarch_tdep types to <arch>_gdbarch_tdep, and make them inherit from a gdbarch_tdep base class. The inheritance is necessary to be able to pass pointers to all these <arch>_gdbarch_tdep objects to gdbarch_alloc, which takes a pointer to gdbarch_tdep. These objects are never deleted through a base class pointer, so I didn't include a virtual destructor. In the future, if gdbarch objects deletable, I could imagine that the gdbarch_tdep objects could become owned by the gdbarch objects, and then it would become useful to have a virtual destructor (so that the gdbarch object can delete the owned gdbarch_tdep object). But that's not necessary right now. It turns out that RISC-V already has a gdbarch_tdep that is non-default-constructible, so that provides a good motivation for this change. Most changes are fairly straightforward, mostly needing to add some casts all over the place. There is however the xtensa architecture, doing its own little weird thing to define its gdbarch_tdep. I did my best to adapt it, but I can't test those changes. Change-Id: Ic001903f91ddd106bd6ca09a79dabe8df2d69f3b
Diffstat (limited to 'gdb/i386-tdep.h')
-rw-r--r--gdb/i386-tdep.h136
1 files changed, 68 insertions, 68 deletions
diff --git a/gdb/i386-tdep.h b/gdb/i386-tdep.h
index ee7655e..8f1819b 100644
--- a/gdb/i386-tdep.h
+++ b/gdb/i386-tdep.h
@@ -57,206 +57,206 @@ enum struct_return
};
/* i386 architecture specific information. */
-struct gdbarch_tdep
+struct i386_gdbarch_tdep : gdbarch_tdep
{
/* General-purpose registers. */
- int *gregset_reg_offset;
- int gregset_num_regs;
- size_t sizeof_gregset;
+ int *gregset_reg_offset = 0;
+ int gregset_num_regs = 0;
+ size_t sizeof_gregset = 0;
/* Floating-point registers. */
- size_t sizeof_fpregset;
+ size_t sizeof_fpregset = 0;
/* Register number for %st(0). The register numbers for the other
registers follow from this one. Set this to -1 to indicate the
absence of an FPU. */
- int st0_regnum;
+ int st0_regnum = 0;
/* Number of MMX registers. */
- int num_mmx_regs;
+ int num_mmx_regs = 0;
/* Register number for %mm0. Set this to -1 to indicate the absence
of MMX support. */
- int mm0_regnum;
+ int mm0_regnum = 0;
/* Number of pseudo YMM registers. */
- int num_ymm_regs;
+ int num_ymm_regs = 0;
/* Register number for %ymm0. Set this to -1 to indicate the absence
of pseudo YMM register support. */
- int ymm0_regnum;
+ int ymm0_regnum = 0;
/* Number of AVX512 OpMask registers (K-registers) */
- int num_k_regs;
+ int num_k_regs = 0;
/* Register number for %k0. Set this to -1 to indicate the absence
of AVX512 OpMask register support. */
- int k0_regnum;
+ int k0_regnum = 0;
/* Number of pseudo ZMM registers ($zmm0-$zmm31). */
- int num_zmm_regs;
+ int num_zmm_regs = 0;
/* Register number for %zmm0. Set this to -1 to indicate the absence
of pseudo ZMM register support. */
- int zmm0_regnum;
+ int zmm0_regnum = 0;
/* Number of byte registers. */
- int num_byte_regs;
+ int num_byte_regs = 0;
/* Register pseudo number for %al. */
- int al_regnum;
+ int al_regnum = 0;
/* Number of pseudo word registers. */
- int num_word_regs;
+ int num_word_regs = 0;
/* Register number for %ax. */
- int ax_regnum;
+ int ax_regnum = 0;
/* Number of pseudo dword registers. */
- int num_dword_regs;
+ int num_dword_regs = 0;
/* Register number for %eax. Set this to -1 to indicate the absence
of pseudo dword register support. */
- int eax_regnum;
+ int eax_regnum = 0;
/* Number of core registers. */
- int num_core_regs;
+ int num_core_regs = 0;
/* Number of SSE registers. */
- int num_xmm_regs;
+ int num_xmm_regs = 0;
/* Number of SSE registers added in AVX512. */
- int num_xmm_avx512_regs;
+ int num_xmm_avx512_regs = 0;
/* Register number of XMM16, the first XMM register added in AVX512. */
- int xmm16_regnum;
+ int xmm16_regnum = 0;
/* Number of YMM registers added in AVX512. */
- int num_ymm_avx512_regs;
+ int num_ymm_avx512_regs = 0;
/* Register number of YMM16, the first YMM register added in AVX512. */
- int ymm16_regnum;
+ int ymm16_regnum = 0;
/* Bits of the extended control register 0 (the XFEATURE_ENABLED_MASK
register), excluding the x87 bit, which are supported by this GDB. */
- uint64_t xcr0;
+ uint64_t xcr0 = 0;
/* Offset of XCR0 in XSAVE extended state. */
- int xsave_xcr0_offset;
+ int xsave_xcr0_offset = 0;
/* Register names. */
- const char * const *register_names;
+ const char * const *register_names = nullptr;
/* Register number for %ymm0h. Set this to -1 to indicate the absence
of upper YMM register support. */
- int ymm0h_regnum;
+ int ymm0h_regnum = 0;
/* Upper YMM register names. Only used for tdesc_numbered_register. */
- const char * const *ymmh_register_names;
+ const char * const *ymmh_register_names = nullptr;
/* Register number for %ymm16h. Set this to -1 to indicate the absence
of support for YMM16-31. */
- int ymm16h_regnum;
+ int ymm16h_regnum = 0;
/* YMM16-31 register names. Only used for tdesc_numbered_register. */
- const char * const *ymm16h_register_names;
+ const char * const *ymm16h_register_names = nullptr;
/* Register number for %bnd0r. Set this to -1 to indicate the absence
bound registers. */
- int bnd0r_regnum;
+ int bnd0r_regnum = 0;
/* Register number for pseudo register %bnd0. Set this to -1 to indicate the absence
bound registers. */
- int bnd0_regnum;
+ int bnd0_regnum = 0;
/* Register number for %bndcfgu. Set this to -1 to indicate the absence
bound control registers. */
- int bndcfgu_regnum;
+ int bndcfgu_regnum = 0;
/* MPX register names. Only used for tdesc_numbered_register. */
- const char * const *mpx_register_names;
+ const char * const *mpx_register_names = nullptr;
/* Register number for %zmm0h. Set this to -1 to indicate the absence
of ZMM_HI256 register support. */
- int zmm0h_regnum;
+ int zmm0h_regnum = 0;
/* OpMask register names. */
- const char * const *k_register_names;
+ const char * const *k_register_names = nullptr;
/* ZMM register names. Only used for tdesc_numbered_register. */
- const char * const *zmmh_register_names;
+ const char * const *zmmh_register_names = nullptr;
/* XMM16-31 register names. Only used for tdesc_numbered_register. */
- const char * const *xmm_avx512_register_names;
+ const char * const *xmm_avx512_register_names = nullptr;
/* YMM16-31 register names. Only used for tdesc_numbered_register. */
- const char * const *ymm_avx512_register_names;
+ const char * const *ymm_avx512_register_names = nullptr;
/* Number of PKEYS registers. */
- int num_pkeys_regs;
+ int num_pkeys_regs = 0;
/* Register number for PKRU register. */
- int pkru_regnum;
+ int pkru_regnum = 0;
/* PKEYS register names. */
- const char * const *pkeys_register_names;
+ const char * const *pkeys_register_names = nullptr;
/* Register number for %fsbase. Set this to -1 to indicate the
absence of segment base registers. */
- int fsbase_regnum;
+ int fsbase_regnum = 0;
/* Target description. */
- const struct target_desc *tdesc;
+ const struct target_desc *tdesc = nullptr;
/* Register group function. */
- gdbarch_register_reggroup_p_ftype *register_reggroup_p;
+ gdbarch_register_reggroup_p_ftype *register_reggroup_p = nullptr;
/* Offset of saved PC in jmp_buf. */
- int jb_pc_offset;
+ int jb_pc_offset = 0;
/* Convention for returning structures. */
- enum struct_return struct_return;
+ enum struct_return struct_return {};
/* Address range where sigtramp lives. */
- CORE_ADDR sigtramp_start;
- CORE_ADDR sigtramp_end;
+ CORE_ADDR sigtramp_start = 0;
+ CORE_ADDR sigtramp_end = 0;
/* Detect sigtramp. */
- int (*sigtramp_p) (struct frame_info *);
+ int (*sigtramp_p) (struct frame_info *) = nullptr;
/* Get address of sigcontext for sigtramp. */
- CORE_ADDR (*sigcontext_addr) (struct frame_info *);
+ CORE_ADDR (*sigcontext_addr) (struct frame_info *) = nullptr;
/* Offset of registers in `struct sigcontext'. */
- int *sc_reg_offset;
- int sc_num_regs;
+ int *sc_reg_offset = 0;
+ int sc_num_regs = 0;
/* Offset of saved PC and SP in `struct sigcontext'. Usage of these
is deprecated, please use `sc_reg_offset' instead. */
- int sc_pc_offset;
- int sc_sp_offset;
+ int sc_pc_offset = 0;
+ int sc_sp_offset = 0;
/* ISA-specific data types. */
- struct type *i386_mmx_type;
- struct type *i386_ymm_type;
- struct type *i386_zmm_type;
- struct type *i387_ext_type;
- struct type *i386_bnd_type;
+ struct type *i386_mmx_type = nullptr;
+ struct type *i386_ymm_type = nullptr;
+ struct type *i386_zmm_type = nullptr;
+ struct type *i387_ext_type = nullptr;
+ struct type *i386_bnd_type = nullptr;
/* Process record/replay target. */
/* The map for registers because the AMD64's registers order
in GDB is not same as I386 instructions. */
- const int *record_regmap;
+ const int *record_regmap = nullptr;
/* Parse intx80 args. */
- int (*i386_intx80_record) (struct regcache *regcache);
+ int (*i386_intx80_record) (struct regcache *regcache) = nullptr;
/* Parse sysenter args. */
- int (*i386_sysenter_record) (struct regcache *regcache);
+ int (*i386_sysenter_record) (struct regcache *regcache) = nullptr;
/* Parse syscall args. */
- int (*i386_syscall_record) (struct regcache *regcache);
+ int (*i386_syscall_record) (struct regcache *regcache) = nullptr;
/* Regsets. */
- const struct regset *fpregset;
+ const struct regset *fpregset = nullptr;
};
/* Floating-point registers. */