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| author | Yao Qi <yao.qi@linaro.org> | 2017-12-08 17:27:03 +0000 |
|---|---|---|
| committer | Yao Qi <yao.qi@linaro.org> | 2017-12-08 17:27:03 +0000 |
| commit | a738ea1d41daeec0cccb4ab6671f4f6d53bd9e18 (patch) | |
| tree | 774250556f5e1468e539e5726014a277d17f6327 /gdb/gdbarch.h | |
| parent | 8e481c3ba86e512b39b16b41de24e87a17f7d968 (diff) | |
| download | gdb-a738ea1d41daeec0cccb4ab6671f4f6d53bd9e18.zip gdb-a738ea1d41daeec0cccb4ab6671f4f6d53bd9e18.tar.gz gdb-a738ea1d41daeec0cccb4ab6671f4f6d53bd9e18.tar.bz2 | |
Clear non-significant bits of address on memory access
ARMv8 supports tagged address, that is, the top one byte in address
is ignored. It is always enabled on aarch64-linux. See
https://www.kernel.org/doc/Documentation/arm64/tagged-pointers.txt
The tag in the tagged address is modeled as non-significant bits in
address, so this patch adds a new gdbarch method significant_addr_bit and
clear the non-significant bits (the top byte in ARMv8) of the virtual
address at the point before passing address to target cache layer. IOW,
the address used in the target cache layer is already cleared.
Before this patch,
(gdb) x/x 0x0000000000411030
0x411030 <global>: 0x00000000
(gdb) x/x 0xf000000000411030
0xf000000000411030: Cannot access memory at address 0xf000000000411030
After this patch,
(gdb) x/x 0x0000000000411030
0x411030 <global>: 0x00000000
(gdb) x/x 0xf000000000411030
0xf000000000411030: 0x00000000
Note that I used address_significant in paddress, but it causes a
regression gdb.base/long_long.exp, because gdb clears the non-significant
bits in address, but test still expects them.
p/a val.oct^M
$24 = 0x2ee53977053977^M
(gdb) FAIL: gdb.base/long_long.exp: p/a val.oct
so I defer the change there.
gdb:
2017-12-08 Yao Qi <yao.qi@linaro.org>
* aarch64-tdep.c (aarch64_gdbarch_init): Install gdbarch
significant_addr_bit.
* gdbarch.sh (significant_addr_bit): New.
* gdbarch.c, gdbarch.h: Re-generated.
* target.c (memory_xfer_partial): Call address_significant.
* utils.c (address_significant): New function.
* utils.h (address_significant): Declare.
2017-12-08 Yao Qi <yao.qi@linaro.org>
gdb/testsuite:
* gdb.arch/aarch64-tagged-pointer.c: New file.
* gdb.arch/aarch64-tagged-pointer.exp: New file.
Diffstat (limited to 'gdb/gdbarch.h')
| -rw-r--r-- | gdb/gdbarch.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/gdb/gdbarch.h b/gdb/gdbarch.h index d2e6b6f..1a654b6 100644 --- a/gdb/gdbarch.h +++ b/gdb/gdbarch.h @@ -677,6 +677,14 @@ typedef CORE_ADDR (gdbarch_addr_bits_remove_ftype) (struct gdbarch *gdbarch, COR extern CORE_ADDR gdbarch_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr); extern void set_gdbarch_addr_bits_remove (struct gdbarch *gdbarch, gdbarch_addr_bits_remove_ftype *addr_bits_remove); +/* On some machines, not all bits of an address word are significant. + For example, on AArch64, the top bits of an address known as the "tag" + are ignored by the kernel, the hardware, etc. and can be regarded as + additional data associated with the address. */ + +extern int gdbarch_significant_addr_bit (struct gdbarch *gdbarch); +extern void set_gdbarch_significant_addr_bit (struct gdbarch *gdbarch, int significant_addr_bit); + /* FIXME/cagney/2001-01-18: This should be split in two. A target method that indicates if the target needs software single step. An ISA method to implement it. |