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| author | Ivo Raisr <ivo.raisr@oracle.com> | 2017-02-05 23:44:03 -0800 |
|---|---|---|
| committer | Jose E. Marchesi <jose.marchesi@oracle.com> | 2017-02-05 23:44:03 -0800 |
| commit | 3f7b46f2daa6c396564d786bda9c81e66d4b9278 (patch) | |
| tree | d2341bb017668a99db92043287aa6bb2fe8c5745 /gdb/doc | |
| parent | de32a80f8f48896d4d07babd8c998789dd07c73d (diff) | |
| download | gdb-3f7b46f2daa6c396564d786bda9c81e66d4b9278.zip gdb-3f7b46f2daa6c396564d786bda9c81e66d4b9278.tar.gz gdb-3f7b46f2daa6c396564d786bda9c81e66d4b9278.tar.bz2 | |
gdb: provide and use sparc{32,64} target description XML files.
gdb/ChangeLog:
2017-02-06 Ivo Raisr <ivo.raisr@oracle.com>
PR tdep/20936
Provide and use sparc32 and sparc64 target description XML files.
* features/sparc/sparc32-cp0.xml, features/sparc/sparc32-cpu.xml,
features/sparc/sparc32-fpu.xml: New files for sparc 32-bit.
* features/sparc/sparc64-cp0.xml, features/sparc/sparc64-cpu.xml,
features/sparc/sparc64-fpu.xml: New files for sparc 64-bit.
* features/sparc/sparc32-solaris.xml: New file.
* features/sparc/sparc64-solaris.xml: New file.
* features/sparc/sparc32-solaris.c: Generated.
* features/sparc/sparc64-solaris.c: Generated.
* sparc-tdep.h: Account for differences in target descriptions.
* sparc-tdep.c (sparc32_register_name): Use target provided registers.
(sparc32_register_type): Use target provided registers.
(validate_tdesc_registers): New function.
(sparc32_gdbarch_init): Use tdesc_has_registers.
Set pseudoregister functions.
* sparc64-tdep.c (sparc64_register_name): Use target provided registers.
(sparc64_register_type): Use target provided registers.
(sparc64_init_abi): Set pseudoregister functions.
gdb/doc/ChangeLog:
2017-02-06 Ivo Raisr <ivo.raisr@oracle.com>
PR tdep/20936
* gdb.texinfo: (Standard Target Features): Document SPARC features.
(Sparc Features): New node.
gdb/testsuite/ChangeLog:
2017-02-06 Ivo Raisr <ivo.raisr@oracle.com>
PR tdep/20936
* gdb.xml/tdesc-regs.exp: Provide sparc core registers for the tests.
Diffstat (limited to 'gdb/doc')
| -rw-r--r-- | gdb/doc/ChangeLog | 6 | ||||
| -rw-r--r-- | gdb/doc/gdb.texinfo | 43 |
2 files changed, 49 insertions, 0 deletions
diff --git a/gdb/doc/ChangeLog b/gdb/doc/ChangeLog index 670e9b7..9b5e140 100644 --- a/gdb/doc/ChangeLog +++ b/gdb/doc/ChangeLog @@ -1,3 +1,9 @@ +2017-02-06 Ivo Raisr <ivo.raisr@oracle.com> + + PR tdep/20936 + * gdb.texinfo: (Standard Target Features): Document SPARC features. + (Sparc Features): New node. + 2017-01-27 Walfred Tedeschi <walfred.tedeschi@intel.com> * gdb.texinfo (i386 Features): Add system segment registers diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo index b9b4c82..a969d1b 100644 --- a/gdb/doc/gdb.texinfo +++ b/gdb/doc/gdb.texinfo @@ -41030,6 +41030,7 @@ registers using the capitalization used in the description. * Nios II Features:: * PowerPC Features:: * S/390 and System z Features:: +* Sparc Features:: * TIC6x Features:: @end menu @@ -41381,6 +41382,48 @@ through @samp{f15} to present the 128-bit wide vector registers contain the 128-bit wide vector registers @samp{v16} through @samp{v31}. +@node Sparc Features +@subsection Sparc Features +@cindex target descriptions, sparc32 features +@cindex target descriptions, sparc64 features +The @samp{org.gnu.gdb.sparc.cpu} feature is required for sparc32/sparc64 +targets. It should describe the following registers: + +@itemize @minus +@item +@samp{g0} through @samp{g7} +@item +@samp{o0} through @samp{o7} +@item +@samp{l0} through @samp{l7} +@item +@samp{i0} through @samp{i7} +@end itemize + +They may be 32-bit or 64-bit depending on the target. + +Also the @samp{org.gnu.gdb.sparc.fpu} feature is required for sparc32/sparc64 +targets. It should describe the following registers: + +@itemize @minus +@item +@samp{f0} through @samp{f31} +@item +@samp{f32} through @samp{f62} for sparc64 +@end itemize + +The @samp{org.gnu.gdb.sparc.cp0} feature is required for sparc32/sparc64 +targets. It should describe the following registers: + +@itemize @minus +@item +@samp{y}, @samp{psr}, @samp{wim}, @samp{tbr}, @samp{pc}, @samp{npc}, +@samp{fsr}, and @samp{csr} for sparc32 +@item +@samp{pc}, @samp{npc}, @samp{state}, @samp{fsr}, @samp{fprs}, and @samp{y} +for sparc64 +@end itemize + @node TIC6x Features @subsection TMS320C6x Features @cindex target descriptions, TIC6x features |