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| author | David Edelsohn <dje.gcc@gmail.com> | 1996-06-30 05:32:38 +0000 |
|---|---|---|
| committer | David Edelsohn <dje.gcc@gmail.com> | 1996-06-30 05:32:38 +0000 |
| commit | 146ff2522856416da4670bc1762c414445bfd96a (patch) | |
| tree | d655ac2565a9f6100d1efe9d589a0c285ea6c3b7 /gdb/doc/gdb.texinfo | |
| parent | 230b079723c63598838d96fbb663dbd14574a700 (diff) | |
| download | gdb-146ff2522856416da4670bc1762c414445bfd96a.zip gdb-146ff2522856416da4670bc1762c414445bfd96a.tar.gz gdb-146ff2522856416da4670bc1762c414445bfd96a.tar.bz2 | |
(all-cfg.text): @set SPARCLET.
(gdb-texinfo): Add sparclet.
(remote.texi): Restore vxworks clobberage. Fix sparclet typos.
Diffstat (limited to 'gdb/doc/gdb.texinfo')
| -rw-r--r-- | gdb/doc/gdb.texinfo | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo index 89bfa83..9ccef79 100644 --- a/gdb/doc/gdb.texinfo +++ b/gdb/doc/gdb.texinfo @@ -753,6 +753,9 @@ in sequential order. The order makes a difference when the @ifset MIPS * MIPS Remote:: @value{GDBN} and MIPS boards @end ifset +@ifset SPARCLET +* Sparclet Remote:: @value{GDBN} and Sparclet boards +@end ifset @ifset SIMS * Simulator:: Simulated CPU target @end ifset @@ -7683,6 +7686,9 @@ configuration of @value{GDBN}; use @code{help target} to list them. @ifset MIPS * MIPS Remote:: @value{GDBN} and MIPS boards @end ifset +@ifset SPARCLET +* Sparclet Remote:: @value{GDBN} and Sparclet boards +@end ifset @ifset SIMS * Simulator:: Simulated CPU target @end ifset |