aboutsummaryrefslogtreecommitdiff
path: root/gdb/config
diff options
context:
space:
mode:
authorSteve Chamberlain <sac@cygnus>1994-11-24 05:59:34 +0000
committerSteve Chamberlain <sac@cygnus>1994-11-24 05:59:34 +0000
commit5f2f280941c6223d0f53a68afe1bdc10751bc3cf (patch)
tree25c4494c9a44a9f0ed5f54e4eea6ae89a1276aee /gdb/config
parentd2fd61a812e28231f53812a02934de33bc2eec2d (diff)
downloadgdb-5f2f280941c6223d0f53a68afe1bdc10751bc3cf.zip
gdb-5f2f280941c6223d0f53a68afe1bdc10751bc3cf.tar.gz
gdb-5f2f280941c6223d0f53a68afe1bdc10751bc3cf.tar.bz2
* remote-e7000.c (HARD_BREAKPOINTS): Reenable.
(BC_BREAKPOINTS): Disable. * sh-tdep.c (print_insn): Cope with big and little endian machines. * sh/sh.mt: Use libsim.a * sh/tm-sh.h (TARGET_BYTE_ORDER_SELECTABLE): New (BREAKPOINT): Changed to be byteorder independent.
Diffstat (limited to 'gdb/config')
-rw-r--r--gdb/config/sh/sh.mt8
-rw-r--r--gdb/config/sh/tm-sh.h7
2 files changed, 4 insertions, 11 deletions
diff --git a/gdb/config/sh/sh.mt b/gdb/config/sh/sh.mt
index cc13121..0581244 100644
--- a/gdb/config/sh/sh.mt
+++ b/gdb/config/sh/sh.mt
@@ -1,11 +1,5 @@
# Target: Hitachi Super-H ICE and simulator
-TDEPFILES= sh-tdep.o remote-sim.o interp.o table.o remote-e7000.o ser-e7kpc.o
-
+TDEPFILES= sh-tdep.o remote-sim.o ../sim/sh/libsim.a remote-e7000.o ser-e7kpc.o
over: all
-interp.o:
- cp ../sim/sh/interp.o .
-
-table.o:
- cp ../sim/sh/table.o .
TM_FILE= tm-sh.h
diff --git a/gdb/config/sh/tm-sh.h b/gdb/config/sh/tm-sh.h
index 83152eb..44310da 100644
--- a/gdb/config/sh/tm-sh.h
+++ b/gdb/config/sh/tm-sh.h
@@ -25,7 +25,7 @@ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
/* Define the bit, byte, and word ordering of the machine. */
-#define TARGET_BYTE_ORDER BIG_ENDIAN
+#define TARGET_BYTE_ORDER_SELECTABLE
/* Offset from address of function to start of its code.
@@ -58,9 +58,8 @@ extern CORE_ADDR sh_skip_prologue ();
/* Illegal instruction - used by the simulator for breakpoint
detection */
-#define BREAKPOINT {0xc3, 0xff} /* 0xc3ff is trapa #ff */
-#undef BREAKPOINT
-#define BREAKPOINT {0x00, 0x1b} /* SLEEP */
+#define BREAKPOINT {0xc3, 0xc3} /* 0xc3c3 is trapa #c3, and it works in big
+ and little endian modes */
#define REMOTE_BREAKPOINT { 0xc3, 0x20}
/* If your kernel resets the pc after the trap happens you may need to