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authorJeff Law <law@redhat.com>1995-06-21 04:20:15 +0000
committerJeff Law <law@redhat.com>1995-06-21 04:20:15 +0000
commit5e2f4e2d6f024e3e47a50aa9d1b1895af88615ec (patch)
tree80406fc3414c8b7041c30671e2ec180661644e18 /gdb/config/pa
parent0283d893cb0a4ff786416c0ddec181d818a6e9d1 (diff)
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* config/pa/tm-hppa.h (PSW_*): Define processor status word masks.
(INSTRUCTION_NULLIFIED): Allow specific targets to override. * config/pa/tm-hppao.h (INSTRUCTION_NULLIFIED): Define to work around losing mach kernel behavior.
Diffstat (limited to 'gdb/config/pa')
-rw-r--r--gdb/config/pa/tm-hppao.h23
1 files changed, 23 insertions, 0 deletions
diff --git a/gdb/config/pa/tm-hppao.h b/gdb/config/pa/tm-hppao.h
index aab7274..7df4247 100644
--- a/gdb/config/pa/tm-hppao.h
+++ b/gdb/config/pa/tm-hppao.h
@@ -69,5 +69,28 @@
/* OSF1 does not need the pc space queue restored. */
#define NO_PC_SPACE_QUEUE_RESTORE
+/* The mach kernel uses the recovery counter to implement single
+ stepping. While this greatly simplifies the kernel support
+ necessary for single stepping, it unfortunately does the wrong
+ thing in the presense of a nullified instruction (gives control
+ back two insns after the nullifed insn). This is an artifact
+ of the HP architecture (recovery counter doesn't tick for
+ nullified insns).
+
+ Do our best to avoid losing in such situations. */
+#define INSTRUCTION_NULLIFIED \
+(({ \
+ int ipsw = (int)read_register(IPSW_REGNUM); \
+ if (ipsw & PSW_N) \
+ { \
+ int pcoqt = (int)read_register(PCOQ_TAIL_REGNUM); \
+ write_register(PCOQ_HEAD_REGNUM, pcoqt); \
+ write_register(PCOQ_TAIL_REGNUM, pcoqt + 0x4); \
+ write_register(IPSW_REGNUM, ipsw & ~(PSW_N | PSW_B | PSW_X)); \
+ stop_pc = pcoqt; \
+ } \
+ }), 0)
+
/* It's mostly just the common stuff. */
+
#include "pa/tm-hppa.h"