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| author | Jason Molenda <jmolenda@apple.com> | 1998-04-02 01:01:35 +0000 |
|---|---|---|
| committer | Jason Molenda <jmolenda@apple.com> | 1998-04-02 01:01:35 +0000 |
| commit | 3dcac15f1f3f940d7f5dad402155dec74291432b (patch) | |
| tree | 82d8a2d785d10e447fc91edee7fa44d7e329c71f /gdb/config/ns32k/tm-nbsd.h | |
| parent | 775b60dd73051e3637a07c112da519c1bb193a06 (diff) | |
| download | gdb-3dcac15f1f3f940d7f5dad402155dec74291432b.zip gdb-3dcac15f1f3f940d7f5dad402155dec74291432b.tar.gz gdb-3dcac15f1f3f940d7f5dad402155dec74291432b.tar.bz2 | |
Wed Apr 1 16:30:49 1998 Ian Dall <Ian.Dall@dsto.defence.gov.au>
* ns32k-tdep.c (flip_bytes, ns32k_localcount,
ns32k_get_enter_addr, sign_extend): Restore functions mysteriously
deleted.
* ns32knbsd-nat.c: New (?) file to support fetching and storing
registers on NetBSD hosts.
* nbsd.mh (NATDEPFILES): put ns32knbsd-nat.o instead of
ns32k-nat.o
* ns32km3-nat.c (reg_offset): Get order of floating point
registers correct. Add extra 32382 register offsets.
(REG_ADDRESS): define to point at correct part of thread
state. Use calls to "warning" instead of "message".
* tm-nbsd.h, tm-ns32km3.h (REGISTER_NAMES, NUM_REGS,
REGISTER_BYTES, REGISTER_BYTE): redefine allowing for 32382
fpu registers.
Diffstat (limited to 'gdb/config/ns32k/tm-nbsd.h')
| -rw-r--r-- | gdb/config/ns32k/tm-nbsd.h | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/gdb/config/ns32k/tm-nbsd.h b/gdb/config/ns32k/tm-nbsd.h index 5a0fa32..6e61de3 100644 --- a/gdb/config/ns32k/tm-nbsd.h +++ b/gdb/config/ns32k/tm-nbsd.h @@ -39,3 +39,41 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ ? sigtramp_saved_pc (FRAME) \ : read_memory_integer ((FRAME)->frame + 4, 4)) \ ) + + +/* tm-umax.h assumes a 32082 fpu. We have a 32382 fpu. */ +#undef REGISTER_NAMES +#undef NUM_REGS +#undef REGISTER_BYTES +#undef REGISTER_BYTE +/* Initializer for an array of names of registers. + There should be NUM_REGS strings in this initializer. */ + +#define REGISTER_NAMES {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ + "sp", "fp", "pc", "ps", \ + "fsr", \ + "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7", "xx", \ + } + +#define NUM_REGS 29 + +/* Total amount of space needed to store our copies of the machine's + register state, the array `registers'. */ +#define REGISTER_BYTES \ + ((NUM_REGS - 4) * REGISTER_RAW_SIZE(R0_REGNUM) \ + + 8 * REGISTER_RAW_SIZE(LP0_REGNUM)) + +/* Index within `registers' of the first byte of the space for + register N. */ + +/* This is a bit yuck. The even numbered double precision floating + point long registers occupy the same space as the even:odd numbered + single precision floating point registers, but the extra 32381 fpu + registers are at the end. Doing it this way is compatable for both + 32081 and 32381 equiped machines. */ + +#define REGISTER_BYTE(N) (((N) < LP0_REGNUM? (N)\ + : ((N) - LP0_REGNUM) & 1? (N) - 1 \ + : ((N) - LP0_REGNUM + FP0_REGNUM)) * 4) + |