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authorFaraz Shahbazker <fshahbazker@wavecomp.com>2019-06-19 15:55:04 -0700
committerFaraz Shahbazker <fshahbazker@wavecomp.com>2019-06-25 09:29:55 -0700
commit9b444f9533c38016e4f2de0198c889b13a62d2bc (patch)
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parent5c2c8c694de18370ac6161a21217627ddadeafc7 (diff)
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MIPS/gas: Fix order of instructions in LI macro expansion
When MTHC1 instruction is paired with MTC1 to write a value to a 64-bit FPR, the MTC1 must be executed first, because the semantic definition of MTC1 is not aware that software will be using an MTHC1 to complete the operation, and sets the upper half of the 64-bit FPR to an UNPREDICTABLE value[1]. Fix the order of MTHC1 and MTC1 instructions in LI macro expansion. Modify the expansions to exploit moves from $zero directly by-passing the use of $AT, where ever possible. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Wave Computing, Inc., Document Number: MD00086, Revision 5.04, December 11, 2013, Section 3.2 "Alphabetical List of Instructions", pp. 217. gas/ * config/tc-mips.c (macro) <M_LI>: Re-order MTHC1 with respect to MTC1 and use $0 for either part where possible. * testsuite/gas/mips/li-d.s: Add test cases for non-zero words in double precision constants. * testsuite/gas/mips/li-d.d: Update reference output. * testsuite/gas/mips/micromips@isa-override-1.d: Likewise. * testsuite/gas/mips/mips32r2@isa-override-1.d: Likewise. * testsuite/gas/mips/mips64r2@isa-override-1.d: Likewise.
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