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| author | Lili Cui <lili.cui@intel.com> | 2020-10-14 04:31:54 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2020-10-14 04:31:54 -0700 |
| commit | f64c42a9fb19409bb45d86d4b78f0465980dfcba (patch) | |
| tree | bf5f77acf4027b62a0a97e2e317813b49860165e /gdb/break-catch-throw.c | |
| parent | 8b65b8953af2d49ae1d2d7fcc5b49c5308febbc1 (diff) | |
| download | gdb-f64c42a9fb19409bb45d86d4b78f0465980dfcba.zip gdb-f64c42a9fb19409bb45d86d4b78f0465980dfcba.tar.gz gdb-f64c42a9fb19409bb45d86d4b78f0465980dfcba.tar.bz2 | |
x86: Support Intel UINTR
gas/
* NEWS: Add Intel UINTR.
* config/tc-i386.c (cpu_arch): Add .uintr.
(cpu_noarch): Likewise.
* doc/c-i386.texi: Document .uintr and nouintr.
* testsuite/gas/i386/i386.exp: Run UINTR tests.
* testsuite/gas/i386/x86-64-uintr.d: Likewise.
* testsuite/gas/i386/x86-64-uintr.s: Likewise.
opcodes/
* i386-dis.c (enum): Add
PREFIX_MOD_3_0F01_REG_5_RM_4,
PREFIX_MOD_3_0F01_REG_5_RM_5,
PREFIX_MOD_3_0F01_REG_5_RM_6,
PREFIX_MOD_3_0F01_REG_5_RM_7,
X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
X86_64_0FC7_REG_6_MOD_3_PREFIX_1.
(prefix_table): New instructions (see prefixes above).
(rm_table): Likewise
* i386-gen.c (cpu_flag_init): Add CPU_UINTR_FLAGS,
CPU_ANY_UINTR_FLAGS.
(cpu_flags): Add CpuUINTR.
* i386-opc.h (enum): Add CpuUINTR.
(i386_cpu_flags): Add cpuuintr.
* i386-opc.tbl: Add UINTR insns.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
Diffstat (limited to 'gdb/break-catch-throw.c')
0 files changed, 0 insertions, 0 deletions