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| author | Antoine Tremblay <antoine.tremblay@ericsson.com> | 2015-12-18 11:33:58 -0500 |
|---|---|---|
| committer | Antoine Tremblay <antoine.tremblay@ericsson.com> | 2015-12-18 11:38:45 -0500 |
| commit | cba7e83fda349cbf423fab274f5b8677d8148947 (patch) | |
| tree | a8a80ad33154cf04b036714027196cd978188a8c /gdb/arm-tdep.h | |
| parent | fa5308bdcc4967861d1277b45205c2623b154a64 (diff) | |
| download | gdb-cba7e83fda349cbf423fab274f5b8677d8148947.zip gdb-cba7e83fda349cbf423fab274f5b8677d8148947.tar.gz gdb-cba7e83fda349cbf423fab274f5b8677d8148947.tar.bz2 | |
Share some ARM target dependent code from GDB with GDBServer
This patch is in preparation for software single stepping support on ARM
it shares some functions and definitions that will be needed.
No regressions, tested on ubuntu 14.04 ARMv7 and x86.
With gdbserver-{native,extended} / { -marm -mthumb }
Not tested: wince/bsd build.
gdb/ChangeLog:
* arch/arm.c (bitcount): Move from arm-tdep.c.
(condition_true): Likewise.
* arch/arm.h (Instruction Definitions): Move form arm-tdep.h.
(condition_true): Move defenition from arm-tdep.h.
(bitcount): Likewise.
* arm-tdep.c (condition_true): Move to arch/arm.c.
(bitcount): Likewise.
* arm-tdep.h (Instruction Definitions): Move to arch/arm.h.
* arm-wince-tdep.c: Include arch/arm.h.
* armnbsd-tdep.c: Likewise.
Diffstat (limited to 'gdb/arm-tdep.h')
| -rw-r--r-- | gdb/arm-tdep.h | 29 |
1 files changed, 0 insertions, 29 deletions
diff --git a/gdb/arm-tdep.h b/gdb/arm-tdep.h index 3e06f79..9b8447b 100644 --- a/gdb/arm-tdep.h +++ b/gdb/arm-tdep.h @@ -26,9 +26,6 @@ struct address_space; #include "arch/arm.h" -/* Size of integer registers. */ -#define INT_REGISTER_SIZE 4 - /* Say how long FP registers are. Used for documentation purposes and code readability in this header. IEEE extended doubles are 80 bits. DWORD aligned they use 96 bits. */ @@ -50,32 +47,6 @@ struct address_space; #define NUM_GREGS 16 /* Number of general purpose registers. */ -/* Instruction condition field values. */ -#define INST_EQ 0x0 -#define INST_NE 0x1 -#define INST_CS 0x2 -#define INST_CC 0x3 -#define INST_MI 0x4 -#define INST_PL 0x5 -#define INST_VS 0x6 -#define INST_VC 0x7 -#define INST_HI 0x8 -#define INST_LS 0x9 -#define INST_GE 0xa -#define INST_LT 0xb -#define INST_GT 0xc -#define INST_LE 0xd -#define INST_AL 0xe -#define INST_NV 0xf - -#define FLAG_N 0x80000000 -#define FLAG_Z 0x40000000 -#define FLAG_C 0x20000000 -#define FLAG_V 0x10000000 - -#define CPSR_T 0x20 - -#define XPSR_T 0x01000000 /* Type of floating-point code in use by inferior. There are really 3 models that are traditionally supported (plus the endianness issue), but gcc can |