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| author | Yao Qi <yao.qi@linaro.org> | 2016-02-26 15:00:36 +0000 |
|---|---|---|
| committer | Yao Qi <yao.qi@linaro.org> | 2016-02-26 15:00:36 +0000 |
| commit | 1f33efec7c6d1357d7e867176cfb88942fc513a8 (patch) | |
| tree | e4114d206b2bdceaa19a63bb8d81350c97f49348 /gdb/arm-tdep.c | |
| parent | ce90fefec908ee50ae5a3b22b03447df638a54c1 (diff) | |
| download | gdb-1f33efec7c6d1357d7e867176cfb88942fc513a8.zip gdb-1f33efec7c6d1357d7e867176cfb88942fc513a8.tar.gz gdb-1f33efec7c6d1357d7e867176cfb88942fc513a8.tar.bz2 | |
Record right reg num of thumb special data instructions
When GDB decodes these thumb special data instructions, such as 'mov sp, r7'
the Rd is got incorrectly. According to the arch reference manual, the Rd
is DN:Rdn, in which DN is bit 7 and Rdn is bits 0 to 2. This patch fixes it.
gdb:
2016-02-26 Yao Qi <yao.qi@linaro.org>
* arm-tdep.c (thumb_record_ld_st_reg_offset): Fix the register
number of Rd.
Diffstat (limited to 'gdb/arm-tdep.c')
| -rw-r--r-- | gdb/arm-tdep.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 17f6fc6..bd0ee97 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -11512,10 +11512,10 @@ thumb_record_ld_st_reg_offset (insn_decode_record *thumb_insn_r) } else { - /* Format 8; special data processing insns. */ - reg_src1 = bits (thumb_insn_r->arm_insn, 0, 2); - record_buf[0] = ARM_PS_REGNUM; - record_buf[1] = reg_src1; + /* Format 8; special data processing insns. */ + record_buf[0] = ARM_PS_REGNUM; + record_buf[1] = (bit (thumb_insn_r->arm_insn, 7) << 3 + | bits (thumb_insn_r->arm_insn, 0, 2)); thumb_insn_r->reg_rec_count = 2; } } |