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| author | Yao Qi <yao@codesourcery.com> | 2014-07-01 15:36:44 +0800 |
|---|---|---|
| committer | Yao Qi <yao@codesourcery.com> | 2014-07-11 21:33:50 +0800 |
| commit | 1db01f22f58cc01768dc921a7443a1bad4e48eb5 (patch) | |
| tree | f75b3763a6917069845e9019f3e7dec4eae17a14 /gdb/arm-tdep.c | |
| parent | 3116063bd617de56fbc3bad046a692b1fb363a9d (diff) | |
| download | gdb-1db01f22f58cc01768dc921a7443a1bad4e48eb5.zip gdb-1db01f22f58cc01768dc921a7443a1bad4e48eb5.tar.gz gdb-1db01f22f58cc01768dc921a7443a1bad4e48eb5.tar.bz2 | |
Restrict matching add/sub sp, #imm
Currently, GDB matches both add/sub sp, #imm in prologue and epilogue,
which is not very precise. On the instruction level, the immediate
number in both instruction can't be negative, so 'sub sp, #imm' only
appears in prologue while 'add sp, #imm' only appears in epilogue.
Note that on assembly level, we can write 'add sp, -8', but gas will
translate to 'sub sp, 8' instruction.
This patch is to only match 'sub sp, #imm' in prologue and match
'add sp, #immm' in epilogue. It paves the way for the following
patch.
gdb:
2014-07-11 Yao Qi <yao@codesourcery.com>
* arm-tdep.c (thumb_analyze_prologue): Don't match instruction
'add sp, #imm'.
(thumb_in_function_epilogue_p): Don't match 'sub sp, #imm'.
Diffstat (limited to 'gdb/arm-tdep.c')
| -rw-r--r-- | gdb/arm-tdep.c | 15 |
1 files changed, 5 insertions, 10 deletions
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 8cc60a4..6b1cf3c 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -737,16 +737,11 @@ thumb_analyze_prologue (struct gdbarch *gdbarch, pv_area_store (stack, regs[ARM_SP_REGNUM], 4, regs[regno]); } } - else if ((insn & 0xff00) == 0xb000) /* add sp, #simm OR - sub sp, #simm */ + else if ((insn & 0xff80) == 0xb080) /* sub sp, #imm */ { offset = (insn & 0x7f) << 2; /* get scaled offset */ - if (insn & 0x80) /* Check for SUB. */ - regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], - -offset); - else - regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], - offset); + regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], + -offset); } else if ((insn & 0xf800) == 0xa800) /* add Rd, sp, #imm */ regs[bits (insn, 8, 10)] = pv_add_constant (regs[ARM_SP_REGNUM], @@ -3264,7 +3259,7 @@ thumb_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) found_return = 1; else if (insn == 0x46bd) /* mov sp, r7 */ found_stack_adjust = 1; - else if ((insn & 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */ + else if ((insn & 0xff80) == 0xb000) /* add sp, imm */ found_stack_adjust = 1; else if ((insn & 0xfe00) == 0xbc00) /* pop <registers> */ { @@ -3324,7 +3319,7 @@ thumb_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) if (insn2 == 0x46bd) /* mov sp, r7 */ found_stack_adjust = 1; - else if ((insn2 & 0xff00) == 0xb000) /* add sp, imm or sub sp, imm */ + else if ((insn2 & 0xff80) == 0xb000) /* add sp, imm */ found_stack_adjust = 1; else if ((insn2 & 0xff00) == 0xbc00) /* pop <registers> without PC */ found_stack_adjust = 1; |