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| author | Simon Marchi <simon.marchi@polymtl.ca> | 2021-05-11 17:32:28 -0400 |
|---|---|---|
| committer | Simon Marchi <simon.marchi@polymtl.ca> | 2021-05-11 17:32:38 -0400 |
| commit | f2a883a81e50746dbfb163e7ca15a0c822274f9a (patch) | |
| tree | a35c08c2c125abe9a27e96bf14ab3a2718035792 /gdb/arm-tdep.c | |
| parent | 64f30eb0f8f578b217cedc9afc650832415e98e2 (diff) | |
| download | gdb-f2a883a81e50746dbfb163e7ca15a0c822274f9a.zip gdb-f2a883a81e50746dbfb163e7ca15a0c822274f9a.tar.gz gdb-f2a883a81e50746dbfb163e7ca15a0c822274f9a.tar.bz2 | |
gdb: fix indentation in arm_record_data_proc_misc_ld_str
The scopes under this "if" are over-indented, fix that.
gdb/ChangeLog:
* arm-tdep.c (arm_record_data_proc_misc_ld_str): Fix
indentation.
Change-Id: I84a551793207ca95d0bc4f122e336555c8179c0e
Diffstat (limited to 'gdb/arm-tdep.c')
| -rw-r--r-- | gdb/arm-tdep.c | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 056973f..c473843 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -10302,20 +10302,20 @@ arm_record_data_proc_misc_ld_str (insn_decode_record *arm_insn_r) /* Handle multiply instructions. */ /* MLA, MUL, SMLAL, SMULL, UMLAL, UMULL. */ if (0 == arm_insn_r->opcode || 1 == arm_insn_r->opcode) - { - /* Handle MLA and MUL. */ - record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19); - record_buf[1] = ARM_PS_REGNUM; - arm_insn_r->reg_rec_count = 2; - } - else if (4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode) - { - /* Handle SMLAL, SMULL, UMLAL, UMULL. */ - record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19); - record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15); - record_buf[2] = ARM_PS_REGNUM; - arm_insn_r->reg_rec_count = 3; - } + { + /* Handle MLA and MUL. */ + record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19); + record_buf[1] = ARM_PS_REGNUM; + arm_insn_r->reg_rec_count = 2; + } + else if (4 <= arm_insn_r->opcode && 7 >= arm_insn_r->opcode) + { + /* Handle SMLAL, SMULL, UMLAL, UMULL. */ + record_buf[0] = bits (arm_insn_r->arm_insn, 16, 19); + record_buf[1] = bits (arm_insn_r->arm_insn, 12, 15); + record_buf[2] = ARM_PS_REGNUM; + arm_insn_r->reg_rec_count = 3; + } } else if (9 == arm_insn_r->decode && opcode1 > 0x10) { |