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authorRichard Earnshaw <richard.earnshaw@arm.com>2010-03-31 22:10:07 +0000
committerRichard Earnshaw <richard.earnshaw@arm.com>2010-03-31 22:10:07 +0000
commitd476da0ef37ba5ca612a536c69bfe2b859e17c46 (patch)
tree16612e185ffd3a08045cab3ecbbc6c3a52e94cc3 /gdb/arm-tdep.c
parent77aabdd2d99a9f2171d284147fe8be83e3da3243 (diff)
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* arm-tdep.c (thumb_get_next_pc_raw): Correctly detect TBH
instructions. Use the PC+4 if the base of the TBB or TBH is the PC register.
Diffstat (limited to 'gdb/arm-tdep.c')
-rw-r--r--gdb/arm-tdep.c20
1 files changed, 15 insertions, 5 deletions
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index f6a8436..d4248f9 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -2959,19 +2959,29 @@ thumb_get_next_pc_raw (struct frame_info *frame, CORE_ADDR pc, int insert_bkpt)
else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
{
/* TBB. */
- CORE_ADDR table, offset, length;
+ CORE_ADDR tbl_reg, table, offset, length;
+
+ tbl_reg = bits (inst1, 0, 3);
+ if (tbl_reg == 0x0f)
+ table = pc + 4; /* Regcache copy of PC isn't right yet. */
+ else
+ table = get_frame_register_unsigned (frame, tbl_reg);
- table = get_frame_register_unsigned (frame, bits (inst1, 0, 3));
offset = get_frame_register_unsigned (frame, bits (inst2, 0, 3));
length = 2 * get_frame_memory_unsigned (frame, table + offset, 1);
nextpc = pc_val + length;
}
- else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
+ else if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
{
/* TBH. */
- CORE_ADDR table, offset, length;
+ CORE_ADDR tbl_reg, table, offset, length;
+
+ tbl_reg = bits (inst1, 0, 3);
+ if (tbl_reg == 0x0f)
+ table = pc + 4; /* Regcache copy of PC isn't right yet. */
+ else
+ table = get_frame_register_unsigned (frame, tbl_reg);
- table = get_frame_register_unsigned (frame, bits (inst1, 0, 3));
offset = 2 * get_frame_register_unsigned (frame, bits (inst2, 0, 3));
length = 2 * get_frame_memory_unsigned (frame, table + offset, 2);
nextpc = pc_val + length;